STM32F050C4 datasheet(19/97 Pages) STMICROELECTRONICS

19 / 97 page

STM32F050xx

Functional overview

Doc ID 023683 Rev 1

19/97

TIM2, TIM3

STM32F050xx devices feature two synchronizable 4-channel general-purpose timers. TIM2

is based on a 32-bit auto-reload up/downcounter and a 16-bit prescaler. TIM3 is based on a

16-bit auto-reload up/downcounter and a 16-bit prescaler. They feature 4 independent

channels each for input capture/output compare, PWM or one-pulse mode output. This

gives up to 12 input captures/output compares/PWMs on the largest packages.

The TIM2 and TIM3 general-purpose timers can work together or with the TIM1 advanced-

control timer via the Timer Link feature for synchronization or event chaining.

TIM2 and TIM3 both have independent DMA request generation.

These timers are capable of handling quadrature (incremental) encoder signals and the

digital outputs from 1 to 3 hall-effect sensors.

Their counters can be frozen in debug mode.

TIM14

This timer is based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM14 features one single channel for input capture/output compare, PWM or one-pulse

mode output.

Its counter can be frozen in debug mode.

TIM16 and TIM17

These timers are based on a 16-bit auto-reload upcounter and a 16-bit prescaler.

TIM16 and TIM17 feature one single channel for input capture/output compare, PWM or

one-pulse mode output.

TIM16, and TIM17 have a complementary output with dead-time generation and

independent DMA request generation

Their counters can be frozen in debug mode.

3.11.3

Independent watchdog (IWDG)

The independent watchdog is based on an 8-bit prescaler and 12-bit downcounter with user-

defined refresh window. It is clocked from an independent 40 kHz internal RC and as it

operates independently from the main clock, it can operate in Stop and Standby modes. It

can be used either as a watchdog to reset the device when a problem occurs, or as a free

running timer for application timeout management. It is hardware or software configurable

through the option bytes. The counter can be frozen in debug mode.

3.11.4

System window watchdog (WWDG)

The system window watchdog is based on a 7-bit downcounter that can be set as free

running. It can be used as a watchdog to reset the device when a problem occurs. It is

clocked from the APB clock (PCLK). It has an early warning interrupt capability and the

counter can be frozen in debug mode.

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