STM32F050C4 datasheet(77/97 Pages) STMICROELECTRONICS

77 / 97 page

STM32F050xx

Electrical characteristics

Doc ID 023683 Rev 1

77/97

6.3.19

Communication interfaces

2C interface characteristics

Unless otherwise specified, the parameters given in Table 57 are derived from tests

performed under ambient temperature, fPCLK frequency and VDD supply voltage conditions

summarized in Table 15: General operating conditions.

The I

2C interface meets the requirements of the standard I2C communication protocol with

the following restrictions: the I/O pins SDA and SCL are mapped to are not “true” open-

drain. When configured as open-drain, the PMOS connected between the I/O pin and VDD is

disabled, but is still present.

The I

2C characteristics are described in Table 57. Refer also to Section 6.3.13: I/O port

characteristics for more details on the input/output alternate function characteristics (SDA

and SCL).

Table 57.

I2C characteristics(1)

Symbol

Parameter

Standard mode

Fast mode

Fast Mode Plus

Unit

Min

Max

Min

Max

Min

Max

tw(SCLL)

SCL clock low time

4.7

1.3

0.5

µs

tw(SCLH)

SCL clock high time

4.0

0.6

0.26

tsu(SDA)

SDA setup time

250

100

th(SDA)

SDA data hold time

0(3)

3450(2)

0(3)

900(2)

0(4)

450(2)

tr(SDA)

tr(SCL)

SDA and SCL rise time

1000

300

120

tf(SDA)

tf(SCL)

SDA and SCL fall time

300

120

th(STA)

Start condition hold time

4.0

0.6

0.26

µs

tsu(STA)

Repeated Start condition

setup time

4.7

0.6

0.26

tsu(STO)

Stop condition setup time

4.0

0.6

0.26

μs

tw(STO:STA)

Stop to Start condition time

(bus free)

4.7

1.3

0.5

μs

Capacitive load for each bus

line

400

550

The I2C characteristics are the requirements from I2C bus specification rev03. They are guaranteed by design when

I2Cx_TIMING register is correctly programmed (Refer to reference manual). These characteristics are not tested in

production.

The maximum data hold time has only to be met if the interface does not stretch the low period of SCL signal.

The device must internally provide a hold time of at least 300ns for the SDA signal in order to bridge the undefined region

of the falling edge of SCL.

The device must internally provide a hold time of at least 120ns for the SDA signal in order to bridge the undefined region

of the falling edge of SCL.

STM32F050C4 bảng dữ liệu(PDF) 77 Page - STMicroelectronics

STM32F050C4 bảng dữ liệu(HTML) 77 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97

bảng dữ liệu tải về

Link URL