DSPIC33FJ64GS406 datasheet(241/456 Pages) MICROCHIP

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 2009-2012 Microchip Technology Inc.

DS70591E-page 241

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

HS/HC-0

R/W-0

FLTSTAT(1)

CLSTAT(1)

TRGSTAT

FLTIEN

CLIEN

TRGIEN

ITB(3)

MDCS(3)

bit 15

bit 8

R/W-0

U-0

R/W-0

DTC<1:0>

DTCP(4)

—MTBS

CAM(2,3,5)

XPRES(6)

IUE

bit 7

bit 0

Legend:

HC = Hardware Clearable bit

HS = Hardware Settable bit

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15

FLTSTAT: Fault Interrupt Status bit(1)

1 = Fault interrupt is pending

0 = No Fault interrupt is pending

This bit is cleared by setting FLTIEN = 0.

bit 14

CLSTAT: Current-Limit Interrupt Status bit(1)

1 = Current-limit interrupt is pending

0 = No current-limit interrupt is pending

This bit is cleared by setting CLIEN = 0.

bit 13

TRGSTAT: Trigger Interrupt Status bit

1 = Trigger interrupt is pending

0 = No trigger interrupt is pending

This bit is cleared by setting TRGIEN = 0.

bit 12

FLTIEN: Fault Interrupt Enable bit

1 = Fault interrupt is enabled

0 = Fault interrupt is disabled and FLTSTAT bit is cleared

bit 11

CLIEN: Current-Limit Interrupt Enable bit

1 = Current-limit interrupt is enabled

0 = Current-limit interrupt is disabled and CLSTAT bit is cleared

bit 10

TRGIEN: Trigger Interrupt Enable bit

1 = A trigger event generates an interrupt request

0 = Trigger event interrupts are disabled and TRGSTAT bit is cleared

bit 9

ITB: Independent Time Base Mode bit(3)

1 = PHASEx/SPHASEx registers provide time base period for this PWM generator

0 = PTPER register provides timing for this PWM generator

bit 8

MDCS: Master Duty Cycle Register Select bit(3)

1 = MDC register provides duty cycle information for this PWM generator

0 = PDCx and SDCx registers provide duty cycle information for this PWM generator

Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.

2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the

CAM bit is ignored.

3: These bits should not be changed after the PWM is enabled by setting PTEN (PTCON<15>) = 1.

4: For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored.

5: Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase and Dead-Time

registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to

the fastest clock.

6: Configure CLMOD (FCLCONX<8>) = 0 and ITB (PWMCONx<9>) = 1 to operate in External Period

Reset mode.

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