DSPIC33FJ64GS406 datasheet(242/456 Pages) MICROCHIP

242 / 456 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591E-page 242

 2009-2012 Microchip Technology Inc.

bit 7-6

DTC<1:0>: Dead-Time Control bits

11 = Dead-Time Compensation mode

10 = Dead-time function is disabled

01 = Negative dead time is actively applied for Complementary Output mode

00 = Positive dead time is actively applied for all output modes

bit 5

DTCP: Dead-Time Compensation Polarity bit(4)

1 = If DTCMPx = 0, PWMxL is shortened and PWMxH is lengthened

If DTCMPx = 1, PWMxH is shortened and PWMxL is lengthened

0 = If DTCMPx = 0, PWMxH is shortened and PWMLx is lengthened

If DTCMPx = 1, PWMxL is shortened and PWMxH is lengthened

bit 4

Unimplemented: Read as ‘0’

bit 3

MTBS: Master Time Base Select bit

1 = PWM generator uses the secondary master time base for synchronization and the clock source for

the PWM generation logic (if secondary time base is available)

0 = PWM generator uses the primary master time base for synchronization and the clock source for

the PWM generation logic

bit 2

CAM: Center-Aligned Mode Enable bit(2,3,5)

1 = Center-Aligned mode is enabled

0 = Edge-Aligned mode is enabled

bit 1

XPRES: External PWM Reset Control bit(6)

1 = Current-limit source resets the time base for this PWM generator if it is in Independent Time

Base mode

0 = External pins do not affect PWM time base

bit 0

IUE: Immediate Update Enable bit

1 = Updates to the active MDC/PDCx/SDCx registers are immediate

0 = Updates to the active PDCx registers are synchronized to the PWM time base

Note 1: Software must clear the interrupt status here and in the corresponding IFSx bit in the interrupt controller.

2: The Independent Time Base mode (ITB = 1) must be enabled to use Center-Aligned mode. If ITB = 0, the

CAM bit is ignored.

3: These bits should not be changed after the PWM is enabled by setting PTEN (PTCON<15>) = 1.

4: For DTCP to be effective, DTC<1:0> must be set to ‘11’; otherwise, DTCP is ignored.

5: Center-Aligned mode ignores the Least Significant 3 bits of the Duty Cycle, Phase and Dead-Time

registers. The highest Center-Aligned mode resolution available is 8.32 ns with the clock prescaler set to

the fastest clock.

6: Configure CLMOD (FCLCONX<8>) = 0 and ITB (PWMCONx<9>) = 1 to operate in External Period

Reset mode.

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