DSPIC33FJ64GS406 datasheet(238/456 Pages) MICROCHIP

238 / 456 page

dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610

DS70591E-page 238

 2009-2012 Microchip Technology Inc.

STCON2: PWM SECONDARY CLOCK DIVIDER SELECT REGISTER 2

U-0

—

bit 15

bit 8

U-0

R/W-0

—

PCLKDIV<2:0>(1)

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-3

Unimplemented: Read as ‘0’

bit 2-0

PCLKDIV<2:0>: PWM Input Clock Prescaler (Divider) Select bits(1)

111 = Reserved

110 = Divide-by-64, maximum PWM timing resolution

101 = Divide-by-32, maximum PWM timing resolution

100 = Divide-by-16, maximum PWM timing resolution

011 = Divide-by-8, maximum PWM timing resolution

010 = Divide-by-4, maximum PWM timing resolution

001 = Divide-by-2, maximum PWM timing resolution

000 = Divide-by-1, maximum PWM timing resolution (power-on default)

Note 1: These bits should be changed only when PTEN = 0. Changing the clock selection during operation will

yield unpredictable results.

STPER: SECONDARY MASTER TIME BASE PERIOD REGISTER

R/W-1

STPER<15:8>

bit 15

bit 8

R/W-1

R/W-0

STPER<7:0>

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

-n = Value at POR

‘1’ = Bit is set

‘0’ = Bit is cleared

x = Bit is unknown

bit 15-0

STPER<15:0>: Secondary Master Time Base (SMTMR) Period Value bits

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