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dsPIC33FJ64GS406 bảng dữ liệu(PDF) 237 Page - Microchip Technology |
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dsPIC33FJ64GS406 bảng dữ liệu(HTML) 237 Page - Microchip Technology |
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237 / 456 page ![]() 2009-2012 Microchip Technology Inc. DS70591E-page 237 dsPIC33FJ32GS406/606/608/610 and dsPIC33FJ64GS406/606/608/610 REGISTER 16-5: STCON: PWM SECONDARY MASTER TIME BASE CONTROL REGISTER U-0 U-0 U-0 HS/HC-0 R/W-0 R/W-0 R/W-0 R/W-0 — — — SESTAT SEIEN EIPU(1) SYNCPOL SYNCOEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 SYNCEN SYNCSRC<2:0> SEVTPS<3:0> bit 7 bit 0 Legend: HC = Hardware Clearable bit HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as ‘0’ bit 12 SESTAT: Special Event Interrupt Status bit 1 = Secondary Special Event Interrupt is pending 0 = Secondary Special Event Interrupt is not pending bit 11 SEIEN: Special Event Interrupt Enable bit 1 = Secondary Special Event Interrupt is enabled 0 = Secondary Special Event Interrupt is disabled bit 10 EIPU: Enable Immediate Period Updates bit(1) 1 = Active Secondary Period register is updated immediately 0 = Active Secondary Period register updates occur on PWM cycle boundaries bit 9 SYNCPOL: Synchronize Input and Output Polarity bit 1 = SYNCIx/SYNCO2 polarity is inverted (active-low) 0 = SYNCIx/SYNCO2 polarity is active-high bit 8 SYNCOEN: Secondary Master Time Base Synchronization Enable bit 1 = SYNCO2 output is enabled. 0 = SYNCO2 output is disabled bit 7 SYNCEN: External Secondary Master Time Base Synchronization Enable bit 1 = External synchronization of secondary time base is enabled 0 = External synchronization of secondary time base is disabled bit 6-4 SYNCSRC<2:0>: PWM Secondary Time Base Synchronization Source Selection bits 111 = Reserved 101 = Reserved 100 = Reserved 011 = SYNCI4 010 = SYNCI3 001 = SYNCI2 000 = SYNCI1 bit 3-0 SEVTPS<3:0>: PWM Secondary Special Event Trigger Output Postscaler Select bits 1111 = 1:16 Postcale 0001 = 1:2 Postcale • • • 0000 = 1:1 Postscale Note 1: This bit only applies to the secondary master time base period. |
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