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ADP1046AACPZ-R7 bảng dữ liệu(PDF) 63 Page - Analog Devices

tên linh kiện ADP1046AACPZ-R7
Giải thích chi tiết về linh kiện  Digital Controller for Isolated Power Supply Applications
PDF  88 Pages
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ADP1046AACPZ-R7 bảng dữ liệu(HTML) 63 Page - Analog Devices

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Data Sheet
ADP1046A
Rev. 0 | Page 63 of 88
PWM AND SYNCHRONOUS RECTIFIER TIMING REGISTERS
Figure 57 and Table 63 to Table 93 describe the implementation and programming of the seven PWM signals that are output from the
ADP1046A. In general, it is recommended that t1 be set to 0 and that t1 be set as the reference point for the other signals.
tPERIOD
tPERIOD
t14
t11
t13
t12
t9
t10
t7
t8
t6
t1
t5
t3
t4
t2
PWM5 (OUTAUX)
SYNC RECT 2 (SR2)
SYNC RECT 1 (SR1)
PWM4 (OUTD)
PWM3 (OUTC)
PWM2 (OUTB)
PWM1 (OUTA)
Figure 57. PWM Timing Diagram
Table 63. Register 0x3F—OUTAUX Switching Frequency Setting
Bits
Bit Name
R/W
Description
7
Pulse skipping
R/W
Setting this bit enables pulse skipping mode. If the ADP1046A requires a duty cycle lower than
the modulation low limit, pulse skipping is enabled.
6
Pulse skipping zero
PWM
R/W
0 = pulse skipping drives all modulated PWM outputs to 0 V.
1 = sets all modulated edges to t = 0 (the crossing rule set in Register 0x52[0] applies).
[5:0]
Switching frequency
R/W
This register sets the switching frequency of the OUTAUX signal.
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Frequency (kHz)
0
0
0
0
0
0
48.83
0
0
0
0
0
1
50.40
0
0
0
0
1
0
52.08
0
0
0
0
1
1
53.88
0
0
0
1
0
0
55.80
0
0
0
1
0
1
57.87
0
0
0
1
1
0
60.1
0
0
0
1
1
1
62.5
0
0
1
0
0
0
65.1
0
0
1
0
0
1
67.93
0
0
1
0
1
0
71.02
0
0
1
0
1
1
74.4
0
0
1
1
0
0
78.13
0
0
1
1
0
1
82.24
0
0
1
1
1
0
86.81
0
0
1
1
1
1
91.91
0
1
0
0
0
0
97.66
0
1
0
0
0
1
100.81
0
1
0
0
1
0
104.17



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