OR2C04A datasheet(157/192 Pages) ETC

157 / 192 page

Data Sheet

June 1999

ORCA Series 2 FPGAs

Lucent Technologies Inc.

157

Timing Characteristics (continued)

Notes:

If the input buffer is placed in delay mode, the chip hold time to the nearest PFU latch is guaranteed to be 0 if the clock is routed using the

primary clock network; (TJ = all, VDD = all). It should also be noted that any signals routed on the clock lines or using the TRIDI buffers directly

from the input buffer do not get delayed at any time.

The delays for all input buffers assume an input rise/fall time of

≤1 V/ns.

Table 46B. OR2TxxB Programmable I/O Cell Timing Characteristics

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤

+85 °C.

Parameter

Symbol

Speed

Unit

-7

-8

Min

Max

Min

Max

Inputs (TJ = 85 °C, VDD = min)

Input Rise Time

—

500

—

500

Input Fall Time

—

500

—

500

Pad to In Delay

PAD_IN_DEL

—

1.1

—

1.0

Pad to Nearest PFU Latch Output

CHIP_LATCH

—

3.3

—

2.4

Delay Added to General Routing

(input buffer in delay mode for

OR2T15B and smaller devices)

—

6.6

—

6.1

Delay Added to General Routing

(input buffer in delay mode for

OR2T40B)

—

8.9

—

8.2

Delay Added to Direct-FF Routing

(input buffer in delay mode for

OR2T15B and smaller devices)

—

6.4

—

6.0

Delay Added to Direct-FF Routing

(input buffer in delay mode for

OR2T40B)

—

8.7

—

8.0

Outputs (TJ = 85 °C, VDD = min, CL = 50 pF)

PFU CK to Pad Delay (DOUT[3:0] to

PAD):

Fast

Slewlim

Sinklim

DOUT_DEL(F)

DOUT_DEL(SL)

DOUT_DEL(SI)

—

2.8

3.6

8.3

—

2.5

3.3

8.0

Output to Pad Delay (OUT[3:0] to

PAD):

Fast

Slewlim

Sinklim

OUT_DEL(F)

OUT_DEL(SL)

OUT_DEL(SI)

—

2.8

3.6

8.3

—

2.5

3.3

8.0

3-state Enable Delay (TS[3:0] to

PAD):

Fast

Slewlim

Sinklim

TS_DEL(F)

TS_DEL(SL)

TS_DEL(SI)

—

3.0

3.8

9.1

—

2.7

3.4

8.7

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