OR2C04A datasheet(154/192 Pages) ETC

154 / 192 page

Data Sheet

ORCA Series 2 FPGAs

June 1999

154

Lucent Technologies Inc.

Timing Characteristics (continued)

Notes:

The pin-to-pin timing parameters in this table should be used instead of results reported by

ORCA Foundry.

This clock delay is for a fully routed clock tree that uses the primary clock network. It includes both the input buffer delay and the clock routing to

the PFU CLK input. The delay will be reduced if any of the clock branches are not used. The given Setup (Delayed and No delay) and Hold

(Delayed) timing allows the input clock pin to be located in any PIC on any side of the device, but direct I/O

→FF routing must be used. The Hold

(No delay) timing assumes the clock pin is located at one of the four center PICs and direct I/O

→FF routing is used. If it is not located at one of

the four center PICs, this delay must be increased by up to the following amounts: OR2C/2T04A = 5.3%, OR2C/2T06A = 6.4%, OR2C/2T08A =

7.3%, OR2C/2T10A = 9.1%, OR2C/2T12A = 10.8%, OR2C/2T15A = 12.2%, OR2C/2T26A = 16.1%, OR2C/2T40A = 21.2%.

Speed grades of -5, -6, and -7 are for OR2TxxA devices only.

Table 45A. OR2CxxA/OR2TxxA Global Input to Clock Setup/Hold Time (Pin-to-Pin)

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C

≤ TA ≤ 70 °C; Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.

Description

(TJ = all, VDD = all)

Device

Speed

Unit

-2

-3

-4

-5

-6

-7

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Input to CLK (TTL/CMOS)

Setup Time (no delay)

OR2C/2T04A

OR2C/2T06A

OR2C/2T08A

OR2C/2T10A

OR2C/2T12A

OR2C/2T15A

OR2C/2T26A

OR2C/2T40A

0.0

—

0.0

—

0.0

—

0.0

—

0.0

—

0.0

—

Input to CLK (TTL/CMOS)

Setup Time (delayed)

OR2C/2T04A

OR2C/2T06A

OR2C/2T08A

OR2C/2T10A

OR2C/2T12A

OR2C/2T15A

OR2C/2T26A

OR2C/2T40A

5.8

5.7

5.6

5.3

5.2

4.9

7.3

6.8

—

5.5

5.4

5.3

5.0

4.9

4.7

6.9

6.4

—

4.2

4.1

4.0

3.9

3.8

3.6

6.0

5.5

—

4.0

3.9

3.8

3.7

3.6

3.4

5.7

5.2

—

4.1

6.7

6.5

—

4.1

6.0

5.8

—

Input to CLK (TTL/CMOS)

Hold Time (no delay)

OR2C/2T04A

OR2C/2T06A

OR2C/2T08A

OR2C/2T10A

OR2C/2T12A

OR2C/2T15A

OR2C/2T26A

OR2C/2T40A

4.2

4.3

4.5

4.8

5.0

5.4

6.2

7.9

—

4.0

4.1

4.3

4.6

4.8

5.1

5.8

6.8

—

3.8

3.9

4.1

4.4

4.6

4.9

5.6

6.6

—

3.6

3.7

3.9

4.2

4.4

4.7

5.3

6.3

—

4.2

4.6

5.8

—

3.7

4.1

4.9

—

Input to CLK (TTL/CMOS)

Hold Time (delayed)

OR2C/2T04A

OR2C/2T06A

OR2C/2T08A

OR2C/2T10A

OR2C/2T12A

OR2C/2T15A

OR2C/2T26A

OR2C/2T40A

0.0

—

0.0

—

0.0

—

0.0

—

0.0

—

0.0

—

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