OR2C04A datasheet(63/192 Pages) ETC

63 / 192 page

Lucent Technologies Inc.

Data Sheet

June 1999

ORCA Series 2 FPGAs

Estimating Power Dissipation (continued)

PCLK

= [0.69 mW/MHz + (0.38 mW/MHz – Branch)

(20 Branches)

+ (0.022 mW/MHz – PFU) (150 PFUs)

+ (0.006 mW/MHz – SMEM_PFU)

(16 SMEM_PFUs)] [40 MHz]

= 427 mW

PTTL

= 20 x [2.2 mW + (0.17 mW/MHz x 20 MHz

x 20%)]

= 57 mW

PCMOS = 20 x [0.17 mW x 20 MHz x 20%]

= 13 mW

POUT = 30 x [(30 pF + 8.8 pF) x (5.25)2 x 20 MHz

x 20%]

=128 mW

PBID

= 16 x [(50 pF + 8.8 pF) x (5.25)2 x 20 MHz

x 20%]

= 104 mW

TOTAL

= 1.50 W

OR2TxxA

The total operating power dissipated is estimated by

summing the standby (IDDSB), internal, and external

power dissipated. The internal and external power is

the power consumed in the PLCs and PICs, respec-

tively. In general, the standby power is small and may

be neglected. The total operating power is as follows:

PT =

Σ PPLC + Σ PPIC

The internal operating power is made up of two parts:

clock generation and PFU output power. The PFU out-

put power can be estimated based upon the number of

PFU outputs switching when driving an average fan-out

of two:

PPFU = 0.08 mW/MHz

For each PFU output that switches, 0.08 mW/MHz

needs to be multiplied times the frequency (in MHz)

that the output switches. Generally, this can be esti-

mated by using one-half the clock rate, multiplied by

some activity factor; for example, 20%.

The power dissipated by the clock generation circuitry

is based upon four parts: the fixed clock power, the

power/clock branch row or column, the clock power dis-

sipated in each PFU that uses this particular clock, and

the power from the subset of those PFUs that is config-

ured in either of the two synchronous modes (SSPM or

SDPM). Therefore, the clock power can be calculated

for the four parts using the following equations:

OR2T04A Clock Power

= [0.29 mW/MHz

+ (0.10 mW/MHz – Branch) (# Branches)

+ (0.01 mW/MHz – PFU) (# PFUs)

+ (0.003 mW/MHz – SMEM_PFU)

(# SMEM_PFUs)] fCLK

For a quick estimate, the worst-case (typical circuit)

OR2T04A clock power

≈ 1.8 mW/MHz.

OR2T06A Clock Power

= [0.30 mW/MHz

+ (0.11 mW/MHz – Branch) (# Branches)

+ (0.01 mW/MHz – PFU) (# PFUs)

+ (0.003 mW/MHz – SMEM_PFU)

(# SMEM_PFUs)] fCLK

For a quick estimate, the worst-case (typical circuit)

OR2T06A clock power

≈ 2.4 mW/MHz.

OR2T08A Clock Power

= [0.31 mW/MHz

+ (0.12 mW/MHz – Branch) (# Branches)

+ (0.01 mW/MHz – PFU) (# PFUs)

+ (0.003 mW/MHz – SMEM_PFU)

(# SMEM_PFUs)] fCLK

For a quick estimate, the worst-case (typical circuit)

OR2T08A clock power

≈ 3.2 mW/MHz.

OR2T10A Clock Power

= [0.32 mW/MHz

+ (0.14 mW/MHz – Branch) (# Branches)

+ (0.01 mW/MHz – PFU) (# PFUs)

+ (0.003 mW/MHz – SMEM_PFU)

(# SMEM_PFUs)] fCLK

For a quick estimate, the worst-case (typical circuit)

OR2T10A clock power

≈ 4.0 mW/MHz.

OR2T12A Clock Power

= [0.33 mW/MHz

+ (0.15 mW/MHz – Branch) (# Branches)

+ (0.01 mW/MHz – PFU) (# PFUs)

+ (0.003 mW/MHz – SMEM_PFU)

(# SMEM_PFUs)] fCLK

For a quick estimate, the worst-case (typical circuit)

OR2T12A clock power

≈ 4.9 mW/MHz.

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