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STM32F407IE bảng dữ liệu(PDF) 111 Page - STMicroelectronics

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STM32F405xx, STM32F407xx
Electrical characteristics
Doc ID 022152 Rev 3
111/180
5.3.19
Communications interfaces
I
2C interface characteristics
Unless otherwise specified, the parameters given in Table 52 are derived from tests
performed under the ambient temperature, fPCLK1 frequency and VDD supply voltage
conditions summarized in Table 13.
The STM32F405xx and STM32F407xx I
2C interface meets the requirements of the
standard I
2C communication protocol with the following restrictions: the I/O pins SDA and
SCL are mapped to are not “true” open-drain. When configured as open-drain, the PMOS
connected between the I/O pin and VDD is disabled, but is still present.
The I
2C characteristics are described in Table 52. Refer also to Section 5.3.16: I/O port
characteristics for more details on the input/output alternate function characteristics (SDA
and SCL).
Table 51.
Characteristics of TIMx connected to the APB2 domain(1)
1.
TIMx is used as a general term to refer to the TIM1, TIM8, TIM9, TIM10, and TIM11 timers.
Symbol
Parameter
Conditions
Min
Max
Unit
tres(TIM)
Timer resolution time
AHB/APB2
prescaler distinct
from 1, fTIMxCLK =
168 MHz
1-
tTIMxCLK
5.95
-
ns
AHB/APB2
prescaler = 1,
fTIMxCLK = 84 MHz
1-
tTIMxCLK
11.9
-
ns
fEXT
Timer external clock
frequency on CH1 to CH4
fTIMxCLK = 168 MHz
APB2 = 84 MHz
0
fTIMxCLK/2
MHz
084
MHz
ResTIM
Timer resolution
-
16
bit
tCOUNTER
16-bit counter clock
period when internal clock
is selected
1
65536
tTIMxCLK
tMAX_COUNT Maximum possible count
-
32768
tTIMxCLK



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