TUSB7320 datasheet(86/115 Pages) TI1

86 / 115 page

TUSB7320, TUSB7340

SLLSE76J – MARCH 2011 – REVISED MAY 2012

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6.3.11 Port PM Status and Control Register (USB 2.0 Ports)

The TUSB73X0 implements a Port PM Status and Control Register for each port that is implemented. The

number of Port PM Status and Control Registers is the same as the value in the MAX_PORTS field in the

Host Controller Structural Parameters 1 Register (see Section 6.2.3).

Operational Base register offset:404h + (10h*(n-1))), where n = Port Number

Default value: 0000 0000h

Table 6-35. HC Operational Register (Operational Base + 404h + (10h*(n-1))), where n = Port Number

Bit

No.

Reset

State

Bit

No.

Reset

State

Table 6-36. Port PM Status and Control Register (USB 2.0) Description

Bit

Field Name

Access

Description

31:28

PORT_TEST_CTRL

Port Test Control.

27:16

RSVD

Reserved. Returns zeros when read.

15:8

L1_DEV_SLOT

L1 Device Slot.

7:4

HIRD

Host Initiated Resume Duration.

RWE

Remote Wake Enable.

2:0

L1S

L1 Status.

6.3.12 Port Link Info Register

The TUSB73X0 implements a Port Link Info Register for each port USB 3.0 port that is implemented. For

USB 2.0 ports, the Port Link Info Register is reserved and returns zeros when read. The number of Port

Link Info Registers is the same as the value in the MAX_PORTS field in the Host Controller Structural

Parameters 1 Register (see Section 6.2.3).

Operational Base register offset:408h + (10h*(n-1))), where n = Port Number

Default value: 0000 0000h

Table 6-37. HC Operational Register (Operational Base + 408h + (10h*(n-1))), where n = Port Number

Bit

No.

Reset

State

Bit

No.

Reset

State

xHCI MEMORY MAPPED REGISTER SPACE

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