TUSB7320 datasheet(69/115 Pages) TI1

69 / 115 page

TUSB7320, TUSB7340

www.ti.com

SLLSE76J – MARCH 2011 – REVISED MAY 2012

Table 5-9. Bit Descriptions – Uncorrectable Error Severity Register(1) (continued)

Completer Abort Severity.

15†

CPL_ABORT_SEVR †

0 – Error Condition is signaled using ERR_NONFATAL

1 – Error Condition is signaled using ERR_FATAL

Completion Timeout Severity.

14†

CPL_TIMEOUT_SEVR †

0 – Error Condition is signaled using ERR_NONFATAL

1 – Error Condition is signaled using ERR_FATAL

Flow Control Error Severity. 0 – Error Condition is signaled using

13†

FC_ERROR_SEVR †

ERR_NONFATAL1 – Error Condition is signaled using ERR_FATAL

Poisoned TLP Severity.

12†

PSN_TLP_SEVR †

0 – Error Condition is signaled using ERR_NONFATAL

1 – Error Condition is signaled using ERR_FATAL

11:6

RSVD

Reserved. Returns zeros when read.

RSVD

Reserved. Returns ‘1’ when read.

Data Link Protocol Error Severity.

4†

DLL_ERROR_SEVR †

0 – Error Condition is signaled using ERR_NONFATAL

1 – Error Condition is signaled using ERR_FATAL

3:0

RSVD

Reserved. Returns zeros when read.

5.7

correctable Error Severity Register

The Correctable Error Status Register reports the status of individual errors as they occur. Software may

clear these bits only by writing a 1 to the desired location.

PCI Express Extended Register Offset: 110h

Default value: 0000 0000h

Table 5-10. PCI Express Extended Register 110h

Bit

No.

Reset

State

Bit

No.

Reset

State

Table 5-11. Bit Descriptions – Correctable Error Severity Register(1)

Bit

Field Name

Access

Description

31:14

RSVD

Reserved. Returns zeros when read.

Advisory Non-Fatal Error Status. This bit is asserted when an Advisory

13†

ANFES †

rcu

Non-Fatal Error has been reported.

Replay Timer Timeout. This bit is asserted when the replay timer expires

12†

REPLAY_TMOUT †

rcu

for a pending request or completion that has not been acknowledged.

11:9

RSVD

Reserved. Returns zeros when read.

REPLAY_NUM Rollover. This bit is asserted when the replay counter

8†

REPLAY_ROLL †

rcu

rolls over when a pending request or completion has not been

acknowledged.

Bad DLLP Error. This bit is asserted when an 8b/10b error was detected

7†

BAD_DLLP †

rcu

by the PHY during the reception of a DLLP.

Bad TLP Error. This bit is asserted when an 8b/10b error was detected

6†

BAD_TLP †

rcu

by the PHY during the reception of a TLP.

5:1

RSVD

Reserved. Returns zeros when read.

(1)

Bits marked with † are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset

PCI EXPRESS EXTENDED CONFIGURATION SPACE

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