TUSB7320 datasheet(59/115 Pages) TI1

59 / 115 page

TUSB7320, TUSB7340

www.ti.com

SLLSE76J – MARCH 2011 – REVISED MAY 2012

4.63 General Control 2 Register

This register is a read/write register is used to control various functions of the TUSB73X0. This register is

reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset.

Note: For Pass 1.0 of the TUSB73X0 design, this register is read only zeros and has no effect.

PCI register offset: DCh

Default value: 0000 001Bh

Table 4-97. PCI Register DCh

Bit

No.

Reset

State

Bit

No.

Reset

State

Table 4-98. General Control 2 Register Description

Bit

Field Name

Access

Description

31:6

RSVD

Reserved. Returns zeros when read.

L1 Maximum Exit Latency. This field is used to program the maximum

acceptable latency when exiting the L1 state. This is used to set the L1

Acceptable Latency field in the Device capabilities register.

000 – Less than 1µs

001 – 1 µs up to less than 2 µs

5:3†

L1_LATENCY†

010 – 2 µs up to less than 4 µs

011 – 4 µs up to less than 8 µs (default)

100 – 8 µs up to less than 16 µs

101 – 16 µs up to less than 32 µs

110 – 32 µs to 64 µs

111 – more than 64 µs

L0s Maximum Exit Latency. This field is used to program the maximum

acceptable latency when exiting the L0s state. This is used to set the L0s

Acceptable Latency field in the Device capabilities register.

000 – Less than 64 ns

001 – 64 ns up to less than 128 ns

2:0†

L0s_LATENCY†

010 – 128 ns up to less than 256 ns

011 – 256 ns up to less than 512 ns (default)

100 – 512 ns up to less than 1 µs

101 – 1 µs up to less than 2 µs

110 – 2 µs to 4 µs

111 – more than 4 µs

4.64 USB Control Register

This register is a read/write register is used to control USB settings in the TUSB73X0. This register is

reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset.

PCI register offset: E0h

Default value: 0000 0000h

CLASSIC PCI CONFIGURATION SPACE

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