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TUSB7320 bảng dữ liệu(PDF) 62 Page - Texas Instruments |
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TUSB7320 bảng dữ liệu(HTML) 62 Page - Texas Instruments |
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62 / 115 page ![]() TUSB7320, TUSB7340 SLLSE76J – MARCH 2011 – REVISED MAY 2012 www.ti.com Table 4-102. De-Emphasis and Swing Control Register Description(1) Bit Field Name Access Description Port 4 Swing. When the PORT4_SWING_OV bit is set to ‘1’, these bits are used to set the output swing for port 4. For details on the behavior of 31:28† PORT4_SWING† rw the swing signals refer to Table 8-1. For the TUSB7320 Port 4 is not present and these bits have no effect. Port 4 Deemphasis. When the PORT4_DE_OV bit is set to ‘1’, these bits are used to set the de-emphasis value for port 4. For details on the 27:24† PORT4_DE† rw behavior of the swing signals refer to Table 8-2. For the TUSB7320 Port 4 is not present and these bits have no effect. Port 3 Swing. When the PORT3_SWING_OV bit is set to ‘1’ these bits are used to set the output swing for port 3. For details on the behavior of 23:20† PORT3_SWING† rw the swing signals refer to Table 8-1. For the TUSB7320 Port 3 is not present and these bits have no effect. Port 3 Deemphasis. When the PORT3_DE_OV bit is set to ‘1’ these bits are used to set the de-emphasis value for port 3. For details on the 19:16† PORT3_DE† rw behavior of the swing signals refer to Table 8-2. For the TUSB7320 Port 3 is not present and these bits have no effect. Port 2 Swing. When the PORT2_SWING_OV bit is set to ‘1’, these bits 15:12† PORT2_SWING† rw are used to set the output swing for port 2.For details on the behavior of the swing signals refer to Table 8-1. Port 2 Deemphasis. When the PORT2_DE_OV bit is set to ‘1’ these bits 11:8† PORT2_DE† rw are used to set the de-emphasis value for port 2. For details on the behavior of the swing signals refer to Table 8-2. Port 1 Swing. When the PORT1_SWING_OV bit is set to ‘1’, these bits 7:4† PORT1_SWING† rw are used to set the output swing for port 1. For details on the behavior of the swing signals refer to Table 8-1. Port 1 Deemphasis. When the PORT1_DE_OV bit is set to ‘1’, these bits 3:0† PORT1_DE† rw are used to set the de-emphasis value for port 1. For details on the behavior of the swing signals refer to Table 8-2. (1) Bits marked with † are reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset 4.66 Equalizer Control Register This register is used to control the equalizer settings for each of the USB 3.0 ports when the default setting is overridden through the Custom PHY Transmit/Receive Control Register. This register is reset by a PCI Express reset (PERST#), a GRST#, or the internally-generated power-on reset. PCI register offset: E8h Register type:Read/Write Default value: 0000 0000h Table 4-103. PCI Register E8h Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 No. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 State Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 No. Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 State 62 CLASSIC PCI CONFIGURATION SPACE Copyright © 2011–2012, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): TUSB7320 TUSB7340 |
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