TFP410-EP

PanelBus

™ DIGITAL TRANSMITTER

SGLS344A − JULY 2006 − REVISED MAY 2011

19

POST OFFICE BOX 655303

register descriptions (continued)

RESERVED

Sub-Address = 07−05

Read Only

Default = 0x641400

7

6

5

4

3

2

1

0

RESERVED[7:0]

RESERVED[7:0]

RESERVED[15:8]

CTL_1_MODE

Sub-Address = 08

Read/Write

Default = 0xBE

7

6

5

4

3

2

1

0

RSVD

TDIS

VEN

HEN

DSEL

BSEL

EDGE

PD

PD: This read/write register contains the power-down mode.

0: Power down (default after RESET)

1: Normal operation

EDGE: This read/write register contains the edge select mode.

0: Input data latches to the falling edge of IDCK+

1: Input data latches to the rising edge of IDCK+

BSEL: This read/write register contains the input bus select mode.

0: 12-bit operation with dual-edge clock

1: 24-bit operation with single-edge clock

input clock mode. In the high-swing mode, DSEL is a don’t care since IDCK is always single-ended.

HEN: This read/write register contains the horizontal sync enable mode.

0: HSYNC input is transmitted as a fixed low.

1: HSYNC input is transmitted in its original state.

VEN: This read/write register contains the vertical sync enable mode.

0: VSYNC input is transmitted as a fixed low.

1: VSYNC input is transmitted in its original state.

TDIS: This read/write register contains the TMDS disable mode.

0: TMDS circuitry enable state is determined by PD.

1: TMDS circuitry is disabled.

CTL_2_MODE

Sub-Address = 09

Read/Write

Default = 0x00

7

6

5

4

3

2

1

0

VLOW

MSEL[3:1]

TSEL

RSEN

HTPLG

MDI

MDI: This read/write register contains the monitor detect interrupt mode.

0: Detected logic level change in detection signal (to clear, write one to this bit)

1: Logic level remains the same.