MMA8652FC datasheet(61/77 Pages) FREESCALE

61 / 77 page

MMA8652FC

Sensors

Freescale Semiconductor, Inc.

6.13

System and control registers

NOTE

Except for STANDBY mode selection, the device must be in STANDBY mode to change any

of the fields within CTRL_REG1 (0x2A).

6.13.1

0x2A: CTRL_REG1 System Control 1 register

CTRL_REG1 register configures the Auto-WAKE sample frequency, output data rate selection, and enables the fast-read mode

and STANDBY/ACTIVE mode selection.

DR[2:0] bits select the Output Data Rate (ODR) for acceleration samples in WAKE mode. The default value is 000 for a data rate

of 800 Hz.

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

ASLP_RATE1

ASLP_RATE0

DR2

DR1

DR0

—

F_READ

ACTIVE

Figure 54. 0x2A CTRL_REG1 register (Read/Write)

Table 62. CTRL_REG1 register

Bit(s)

Field

Description

7–6

ASLP_RATE[1:0]

Configures the Auto-WAKE sample frequency when the device is in SLEEP Mode.

See Table 63.

00 (default)

5–3

DR[2:0]

Data rate selection

See Table 64.

000 (default)

1F_READ

Fast-read mode: Data format is limited to single byte

0 Normal mode (default)

1 Fast Read Mode

0ACTIVE

Full-scale selection

0 STANDBY mode (default)

1 ACTIVE mode

Table 63. SLEEP mode rates

ASLP_RATE1

ASLP_RATE0

Frequency (Hz)

Notes

When the device is in Auto-SLEEP mode, the system ODR and the

data rate for all the system functional blocks are overridden by the data

rate set by the ASLP_RATE field.

12.5

6.25

1.56

Table 64. System output data rate selection

DR2

DR1

DR0

ODR

(Hz)

Period

(ms)

Notes

800

1.25

default

400

2.5

200

100

12.5

6.25

160

1.56

640

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