MK30DX64VMB7 datasheet(20/72 Pages) FREESCALE

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Table 9. General switching specifications

Symbol

Description

Min.

Max.

Unit

Notes

GPIO pin interrupt pulse width (digital glitch filter

disabled) — Synchronous path

1.5

—

Bus clock

cycles

1, 2

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter enabled) — Asynchronous path

100

—

GPIO pin interrupt pulse width (digital glitch filter

disabled, analog filter disabled) — Asynchronous path

—

External reset pulse width (digital glitch filter disabled)

100

—

Mode select (EZP_CS) hold time after reset

deassertion

—

Bus clock

cycles

Port rise and fall time (high drive strength)

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

—

Port rise and fall time (low drive strength)

• Slew disabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

• Slew enabled

• 1.71 ≤ VDD ≤ 2.7V

• 2.7 ≤ VDD ≤ 3.6V

—

1. This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may or

may not be recognized. In Stop, VLPS, LLS, and VLLSx modes, the synchronizer is bypassed so shorter pulses can be

recognized in that case.

2. The greater synchronous and asynchronous timing must be met.

3. This is the minimum pulse width that is guaranteed to be recognized as a pin interrupt request in Stop, VLPS, LLS, and

VLLSx modes.

4. 75pF load

5. 15pF load

5.4 Thermal specifications

General

K30 Sub-Family Data Sheet, Rev. 2, 4/2012.

Freescale Semiconductor, Inc.

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