MK30DX64VMB7 datasheet(57/72 Pages) FREESCALE

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S10

I2S_MCLK (output)

I2S_TX_BCLK/

I2S_RX_BCLK (output)

I2S_TX_FS/

I2S_RX_FS (output)

I2S_TX_FS/

I2S_RX_FS (input)

I2S_TXD

I2S_RXD

Figure 23. I2S/SAI timing — master modes

Table 40. I2S/SAI slave mode timing in Normal Run, Wait and Stop modes

(full voltage range)

Num.

Characteristic

Min.

Max.

Unit

Operating voltage

1.71

3.6

S11

I2S_TX_BCLK/I2S_RX_BCLK cycle time (input)

—

S12

I2S_TX_BCLK/I2S_RX_BCLK pulse width high/low

(input)

45%

55%

MCLK period

S13

I2S_TX_FS/I2S_RX_FS input setup before

I2S_TX_BCLK/I2S_RX_BCLK

5.8

—

S14

I2S_TX_FS/I2S_RX_FS input hold after

I2S_TX_BCLK/I2S_RX_BCLK

—

S15

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output valid

—

20.6

S16

I2S_TX_BCLK to I2S_TXD/I2S_TX_FS output invalid

—

S17

I2S_RXD setup before I2S_RX_BCLK

5.8

—

S18

I2S_RXD hold after I2S_RX_BCLK

—

S19

I2S_TX_FS input assertion to I2S_TXD output valid1

—

1. Applies to first bit in each frame and only if the TCR4[FSE] bit is clear

Peripheral operating requirements and behaviors

K30 Sub-Family Data Sheet, Rev. 2, 4/2012.

Freescale Semiconductor, Inc.

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