MK30DX64VMB7 datasheet(27/72 Pages) FREESCALE

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Table 13. MCG specifications (continued)

Symbol

Description

Min.

Typ.

Max.

Unit

Notes

fdco_t_DMX3

DCO output

frequency

Low range (DRS=00)

732 × ffll_ref

—

23.99

—

MHz

4, 5

Mid range (DRS=01)

1464 × ffll_ref

—

47.97

—

MHz

Mid-high range (DRS=10)

2197 × ffll_ref

—

71.99

—

MHz

High range (DRS=11)

2929 × ffll_ref

—

95.98

—

MHz

Jcyc_fll

FLL period jitter

• fVCO = 48 MHz

• fVCO = 98 MHz

—

180

150

—

tfll_acquire

FLL target frequency acquisition time

—

PLL

fvco

VCO operating frequency

48.0

—

100

MHz

Ipll

PLL operating current

• PLL @ 96 MHz (fosc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 48)

—

1060

—

µA

Ipll

PLL operating current

• PLL @ 48 MHz (fosc_hi_1 = 8 MHz, fpll_ref =

2 MHz, VDIV multiplier = 24)

—

600

—

µA

fpll_ref

PLL reference frequency range

2.0

—

4.0

MHz

Jcyc_pll

PLL period jitter (RMS)

• fvco = 48 MHz

• fvco = 100 MHz

—

120

—

Jacc_pll

PLL accumulated jitter over 1µs (RMS)

• fvco = 48 MHz

• fvco = 100 MHz

—

1350

600

—

Dlock

Lock entry frequency tolerance

± 1.49

—

± 2.98

Dunl

Lock exit frequency tolerance

± 4.47

—

± 5.97

tpll_lock

Lock detector detection time

—

150 × 10-6

+ 1075(1/

fpll_ref)

1. This parameter is measured with the internal reference (slow clock) being used as a reference to the FLL (FEI clock

mode).

2. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=0.

3. The resulting system clock frequencies should not exceed their maximum specified values. The DCO frequency deviation

(

Δfdco_t) over voltage and temperature should be considered.

4. These typical values listed are with the slow internal reference clock (FEI) using factory trim and DMX32=1.

5. The resulting clock frequency must not exceed the maximum specified clock frequency of the device.

Peripheral operating requirements and behaviors

K30 Sub-Family Data Sheet, Rev. 2, 4/2012.

Freescale Semiconductor, Inc.

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