MK30DX64VMB7 datasheet(52/72 Pages) FREESCALE

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6.7 Timers

See General switching specifications.

6.8 Communication interfaces

6.8.1 CAN switching specifications

See General switching specifications.

6.8.2 DSPI switching specifications (limited voltage range)

The DMA Serial Peripheral Interface (DSPI) provides a synchronous serial bus with

master and slave operations. Many of the transfer attributes are programmable. The tables

below provide DSPI timing characteristics for classic SPI timing modes. Refer to the

DSPI chapter of the Reference Manual for information on the modified transfer formats

used for communicating with slower peripheral devices.

Table 35. Master mode DSPI timing (limited voltage range)

Num

Description

Min.

Max.

Unit

Notes

Operating voltage

2.7

3.6

Frequency of operation

—

MHz

DS1

DSPI_SCK output cycle time

2 x tBUS

—

DS2

DSPI_SCK output high/low time

(tSCK/2) − 2 (tSCK/2) + 2

DS3

DSPI_PCSn valid to DSPI_SCK delay

(tBUS x 2) −

—

DS4

DSPI_SCK to DSPI_PCSn invalid delay

(tBUS x 2) −

—

DS5

DSPI_SCK to DSPI_SOUT valid

—

8.5

DS6

DSPI_SCK to DSPI_SOUT invalid

−2

—

DS7

DSPI_SIN to DSPI_SCK input setup

—

DS8

DSPI_SCK to DSPI_SIN input hold

—

1. The delay is programmable in SPIx_CTARn[PSSCK] and SPIx_CTARn[CSSCK].

2. The delay is programmable in SPIx_CTARn[PASC] and SPIx_CTARn[ASC].

Peripheral operating requirements and behaviors

K30 Sub-Family Data Sheet, Rev. 2, 4/2012.

Freescale Semiconductor, Inc.

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