AFS090 datasheet(142/334 Pages) MICROSEMI

142 / 334 page

Device Architecture

2- 12 6

R e v isio n 2

Examples

Calculating Accuracy for an Uncalibrated Analog Channel

Formula

For a given prescaler range, EQ 30 gives the output voltage.

Output Voltage = (Channel Output Offset in V) + (Input Voltage x Channel Gain)

EQ 30

where

Channel Output offset in V = Channel Input offset in LSBs x Equivalent voltage per LSB

Channel Gain Factor = 1+ (% Channel Gain / 100)

Example

Input Voltage = 5 V

Chosen Prescaler range = 8 V range

Refer to Table 2-51 on page 2-124.

Max. Output Voltage = (Max Positive input offset) + (Input Voltage x Max Positive Channel Gain)

Max. Positive input offset = (21 LSB) x (8 mV per LSB in 10-bit mode)

Max. Positive input offset = 166 mV

Max. Positive Gain Error = +3%

Max. Positive Channel Gain = 1 + (+3% / 100)

Max. Positive Channel Gain = 1.03

Max. Output Voltage = (166 mV) + (5 V x 1.03)

Max. Output Voltage = 5.316 V

Table 2-53 • Analog Channel Accuracy: Monitoring Standard Positive Voltages

Typical Conditions, TA = 25°C

Input Voltage

(V)

Calibrated Typical Error per Positive Prescaler Setting 1 (%FSR)

Direct ADC 2,3

(%FSR)

16 V (AT)

16 V (12 V)

(AV/AC)

8 V

(AV/AC)

4 V (AT)

4 V

(AV/AC)

2 V

(AV/AC)

1 V

(AV/AC)

VAREF = 2.56 V

3.3

2.5

1.8

1.5

1.2

0.9

Notes:

1. Requires enabling Analog Calibration using SmartGen Analog System Builder. For further details, refer to the

"Temperature, Voltage, and Current Calibration in Fusion FPGAs" chapter of the

Fusion FPGA Fabric User’s Guide.

2. Direct ADC mode using an external VAREF of 2.56V±4.6mV, without Analog Calibration macro.

3. For input greater than 2.56 V, the ADC output will saturate. A higher VAREF or prescaler usage is recommended.

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