AFS090 datasheet(71/334 Pages) MICROSEMI

71 / 334 page

Fusion Family of Mixed Signal FPGAs

R e visio n 2

2 - 55

tSUPGLOSSPRO

Page Loss Protect Setup Time for the Control Logic

1.69

1.93

2.27

tHDPGLOSSPRO

Page Loss Protect Hold Time for the Control Logic

0.00

tSUPGSTAT

Page Status Setup Time for the Control Logic

2.49

2.83

3.33

tHDPGSTAT

Page Status Hold Time for the Control Logic

0.00

tSUOVERWRPG

Over Write Page Setup Time for the Control Logic

1.88

2.14

2.52

tHDOVERWRPG

Over Write Page Hold Time for the Control Logic

0.00

tSULOCKREQUEST

Lock Request Setup Time for the Control Logic

0.87

0.99

1.16

tHDLOCKREQUEST

Lock Request Hold Time for the Control Logic

0.00

tRECARNVM

Reset Recovery Time

0.94

1.07

1.25

tREMARNVM

Reset Removal Time

0.00

tMPWARNVM

Asynchronous Reset Minimum Pulse Width for the

Control Logic

10.00

12.50

tMPWCLKNVM

Clock Minimum Pulse Width for the Control Logic

4.00

5.00

tFMAXCLKNVM

Maximum Frequency for Clock for the Control Logic – for

AFS1500/AFS600

80.00

MHz

Maximum Frequency for Clock for the Control Logic – for

AFS250/AFS090

100.00

80.00

MHz

Table 2-25 • Flash Memory Block Timing (continued)

Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V

Parameter

Description

–2

–1

Std.

Units

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