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công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
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AFS090 bảng dữ liệu(PDF) 47 Page - Microsemi Corporation |
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AFS090 bảng dữ liệu(HTML) 47 Page - Microsemi Corporation |
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47 / 334 page  Fusion Family of Mixed Signal FPGAs R e visio n 2 2 - 31 No-Glitch MUX (NGMUX) Positioned downstream from the PLL/CCC blocks, the NGMUX provides a special switching sequence between two asynchronous clock domains that prevents generating any unwanted narrow clock pulses. The NGMUX is used to switch the source of a global between three different clock sources. Allowable inputs are either two PLL/CCC outputs or a PLL/CCC output and a regular net, as shown in Figure 2-24. The GLMUXCFG[1:0] configuration bits determine the source of the CLK inputs (i.e., internal signal or GLC). These are set by SmartGen during design but can also be changed by dynamically reconfiguring the PLL. The GLMUXSEL[1:0] bits control which clock source is passed through the NGMUX to the global network (GL). See Table 2-13. Figure 2-24 • NGMUX Table 2-13 • NGMUX Configuration and Selection Table GLMUXCFG[1:0] GLMUXSEL[1:0] Selected Input Signal MUX Type 00 X 0 GLA 2-to-1 GLMUX X1 GLC 01 X 0 GLA 2-to-1 GLMUX X 1 GLINT Crystal Oscillator RC Oscillator W I/O Ring CCC/PLL Clock I/Os From FPGA Core PLL/ CCC GLINT GLA GLC NGMUX GLMUXCFG[1:0] PWR UP GLMUXSEL[1:0] GL To Clock Rib Driver |
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