AFS090 datasheet(278/334 Pages) MICROSEMI

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DC and Power Characteristics

3- 28

R e visio n 2

Example of Power Calculation

This example considers a shift register with 5,000 storage tiles, including a counter and memory that

stores analog information. The shift register is clocked at 50 MHz and stores and reads information from

a RAM.

The device used is a commercial AFS600 device operating in typical conditions.

The calculation below uses the power calculation methodology previously presented and shows how to

determine the dynamic and static power consumption of resources used in the application.

Also included in the example is the calculation of power consumption in operating, standby, and sleep

modes to illustrate the benefit of power-saving modes.

Global Clock Contribution—PCLOCK

FCLK = 50 MHz

Number of sequential VersaTiles: NS-CELL = 5,000

Estimated number of Spines: NSPINES = 5

Estimated number of Rows: NROW = 313

Operating Mode

PCLOCK = (PAC1 + NSPINE * PAC2 + NROW * PAC3 + NS-CELL * PAC4) * FCLK

PCLOCK = (0.0128 + 5 * 0.0019 + 313 * 0.00081 + 5,000 * 0.00011) * 50

PCLOCK = 41.28 mW

Standby Mode and Sleep Mode

PCLOCK = 0 W

Logic—Sequential Cells, Combinational Cells, and Routing Net Contributions—PS-CELL,

PC-CELL, and PNET

FCLK = 50 MHz

Number of sequential VersaTiles: NS-CELL = 5,000

Number of combinatorial VersaTiles: NC-CELL = 6,000

Estimated toggle rate of VersaTile outputs:

1 = 0.1 (10%)

Operating Mode

PS-CELL = NS-CELL * (PAC5+ (α1 / 2) * PAC6) * FCLK

PS-CELL = 5,000 * (0.00007 + (0.1 / 2) * 0.00029) * 50

PS-CELL = 21.13 mW

PC-CELL = NC-CELL* (α1 / 2) * PAC7 * FCLK

PC-CELL = 6,000 * (0.1 / 2) * 0.00029 * 50

PC-CELL = 4.35 mW

PNET = (NS-CELL + NC-CELL) * (α1 / 2) * PAC8 * FCLK

PNET = (5,000 + 6,000) * (0.1 / 2) * 0.0007 * 50

PNET = 19.25 mW

PLOGIC = PS-CELL + PC-CELL + PNET

PLOGIC = 21.13 mW + 4.35 mW + 19.25 mW

PLOGIC = 44.73 mW

Standby Mode and Sleep Mode

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