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AFS090 bảng dữ liệu(PDF) 236 Page - Microsemi Corporation

tên linh kiện AFS090
Giải thích chi tiết về linh kiện  Fusion Family of Mixed Signal FPGAs
PDF  334 Pages
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nhà sản xuất  MICROSEMI [Microsemi Corporation]
Trang chủ  http://www.microsemi.com
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AFS090 bảng dữ liệu(HTML) 236 Page - Microsemi Corporation

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Device Architecture
2- 22 0
R e v isio n 2
Output Enable Register
Timing Characteristics
Figure 2-139 • Output Enable Register Timing Diagram
50%
Preset
Clear
EOUT
CLK
D_Enable
Enable
tOESUE
50%
50%
tOESUD tOEHD
50%
50%
tOECLKQ
1
0
tOEHE
tOERECPRE
tOEREMPRE
tOERECCLR
tOEREMCLR
tOEWCLR
tOEWPRE
tOEPRE2Q
tOECLR2Q
tOECKMPWH tOECKMPWL
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
50%
Table 2-178 • Output Enable Register Propagation Delays
Commercial Temperature Range Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tOECLKQ
Clock-to-Q of the Output Enable Register
0.44 0.51
0.59
ns
tOESUD
Data Setup Time for the Output Enable Register
0.31 0.36
0.42
ns
tOEHD
Data Hold Time for the Output Enable Register
0.00 0.00
0.00
ns
tOESUE
Enable Setup Time for the Output Enable Register
0.44 0.50
0.58
ns
tOEHE
Enable Hold Time for the Output Enable Register
0.00 0.00
0.00
ns
tOECLR2Q
Asynchronous Clear-to-Q of the Output Enable Register
0.67 0.76
0.89
ns
tOEPRE2Q
Asynchronous Preset-to-Q of the Output Enable Register
0.67 0.76
0.89
ns
tOEREMCLR
Asynchronous Clear Removal Time for the Output Enable Register
0.00 0.00
0.00
ns
tOERECCLR
Asynchronous Clear Recovery Time for the Output Enable Register
0.22 0.25
0.30
ns
tOEREMPRE
Asynchronous Preset Removal Time for the Output Enable Register
0.00 0.00
0.00
ns
tOERECPRE
Asynchronous Preset Recovery Time for the Output Enable Register
0.22 0.25
0.30
ns
tOEWCLR
Asynchronous Clear Minimum Pulse Width for the Output Enable
Register
0.22 0.25
0.30
ns
tOEWPRE
Asynchronous Preset Minimum Pulse Width for the Output Enable
Register
0.22 0.25
0.30
ns
tOECKMPWH Clock Minimum Pulse Width High for the Output Enable Register
0.36 0.41
0.48
ns
tOECKMPWL
Clock Minimum Pulse Width Low for the Output Enable Register
0.32 0.37
0.43
ns
Note:
For the derating values at specific junction temperature and voltage supply levels, refer to Table 3-7 on
page 3-9.



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