MPC5125 datasheet(66/94 Pages) FREESCALE

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MPC5125 Microcontroller Data Sheet, Rev. 4

Electrical and Thermal Characteristics

Freescale Semiconductor

Figure 28. Ethernet Timing Diagram — MII Tx Signal

Figure 29. Ethernet Timing Diagram — MII Async

Table 31. MII Async Signal Timing

Sym

Description

Min

Max

Unit

SpecID

t17

CRS, COL minimum pulse width

1.5

—

TX_CLK Period

A11.17

Table 32. MII Serial Management Channel Signal Timing

Sym

Description

Min

Max

Unit

SpecID

t18

MDC falling edge to MDIO output delay

A11.18

t19

MDIO (input) to MDC rising edge setup

—

A11.19

t20

MDIO (input) to MDC rising edge hold

—

A11.20

t21

MDC pulse width high1

NOTES:

1 MDC is generated by the MPC5125 with a duty cycle of 50% except when MII_SPEED in the FEC MII_SPEED control register

is changed during operation. See the MPC5125 Reference Manual (MPC5125RM).

160

—

A11.21

t22

MDC pulse width low1

160

—

A11.22

t23

MDC period2

2 The MDC period must be set to a value of less than or equal to 2.5 MHz (to be compliant with the IEEE MII characteristic) by

programming the FEC MII_SPEED control register. See the MPC5125 Reference Manual (MPC5125RM).

400

—

A11.23

t12, t16

t11, t15

t9, t13

TX_CLK (Input)

TXD[3:0] (Outputs)

TX_EN

TX_ER

t10, t14

t17

CRS, COL

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