MPC5125 datasheet(34/94 Pages) FREESCALE

34 / 94 page

HRESET

—ALT0

ALT1

ALT2

ALT3

HRESET

—

VDD_IO

1. This pin is an input or

open-drain output, and have

internal pull-up P-FETs. This

pin can not be configured.

5. This pin contains an

enabled internal

schmitt-trigger.

A17

PORESET

—ALT0

ALT1

ALT2

ALT3

PORESET

—

VDD_IO

1. This pin is an input or

open-drain output, and have

internal pull-up P-FETs. This

pin can not be configured.

2. This pin is an input only.

This pin cannot be configured.

5. This pin contains an

enabled internal

schmitt-trigger.

C17

SRESET

—ALT0

ALT1

ALT2

ALT3

SRESET

—

VDD_IO

1. This pin is an input or

open-drain output, and have

internal pull-up P-FETs. This

pin can not be configured.

5. This pin contains an

enabled internal

schmitt-trigger.

A18

Test/Debug

TEST

—

ALT0

ALT1

ALT2

ALT3

TEST

—

VDD_IO

2. This pin is an input only.

This pin cannot be configured.

4. This test pin must be tied to

VSS.

D14

Table 2. MPC5125 Pin Multiplexing (continued)

Pad I/O

Control

Register1

and Offset2

Alternate

Function3

Functions4

Peripheral5

I/O

Direction

Power Domain

Notes

MPC5125 bảng dữ liệu(PDF) 34 Page - Freescale Semiconductor, Inc

MPC5125 bảng dữ liệu(HTML) 34 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

bảng dữ liệu tải về

Link URL