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CS5467 bảng dữ liệu(PDF) 15 Page - Cirrus Logic |
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CS5467 bảng dữ liệu(HTML) 15 Page - Cirrus Logic |
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15 / 46 page ![]() CS5467 DS714F3 15 4.4 DC Offset and Gain Correction The system and chip inherently have gain and offset er- rors which can be removed using the gain and offset registers. (See Section 9. System Calibration on page 40). Each measurement channel has its own registers. For every channel, the output of the IIR filter is added to the offset register and multiplied by the gain register. 4.5 High-pass Filters Optional high-pass filters (HPF in Figures 3 and 4) re- move any DC from the selected signal paths. Subse- quently, DC will also be removed from power, and all low-rate results. (see Figures 5). Each energy channel has a current and voltage path. If an HPF is enabled in only one path, a phase-matching filter (PMF) is applied to the other path which matches the amplitude and phase delay of the HPF in the band of interest, but passes DC. For more information, see 6.5 High-pass Filters on page 20. The HPF filter multi- plexers drive the I1, V1, I2, and V2 result registers. 4.6 Low-Rate Calculations Low-rate results are derived from sample-rate results integrated over N samples, where N is the value stored in the Cycle Count register. The low-rate interval is the sample interval multiplied by N. 4.7 RMS Results The root mean square (RMS in Figure 5) calculations are performed on N instantaneous voltage and current samples, using the formula: I RMS I n n0 = N1 – N --------------------- = 2 |
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