LH28F008SC

8M (1M × 8) Flash Memory

28

SYMBOL

PARAMETER

UNIT

NOTE

MIN.

MAX.

MIN.

MAX.

MIN.

MAX.

t

AVAV

Write Cycle Time

85

90

120

ns

t

PHWL

RP

Going Low

1

1

1

µs

2

t

ELWL

CE

10

10

10

ns

t

WLWH

WE Pulse Width

40

40

40

ns

t

PHHWH

RP

Going High

100

100

100

ns

2

t

VPWH

V

Going High

100

100

100

ns

2

t

AVWH

Address Setup to WE

Going High

40

40

40

ns

3

t

DVWH

Data Setup to WE

Going High

40

40

40

ns

3

t

WHDX

Data Hold from WE High

5

5

5

ns

t

WHAX

Address Hold from

WE High

5

5

5

ns

t

WHEH

CE

10

10

10

ns

t

WHWL

WE Pulse Width High

30

30

30

ns

t

WHRL

WE High to RY

Low

90

90

ns

t

WHGL

Write Recovery before

Read

00

0

ns

t

QVVL

V

RY

00

0

ns

2, 4

t

QVPH

RP

SRD, RY

00

0

ns

2, 4

NOTES:

1. Read timing characteristics during block erase, byte write and lock-bit configuration operations are

the same as during read-only operations. Refer to AC Characteristics for read-only operations.

2. Sampled, not 100% tested.

byte write, or lock-bit configuration success (SR.1/3/4/5 = 0).

5. See Ordering Information for device speeds (valid operational combinations).

6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration)

for testing characteristics.

7. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration)

for testing characters.