LH28F008SC datasheet(19/38 Pages) SHARP

19 / 38 page

8M (1M × 8) Flash Memory

LH28F008SC

Figure 11. Clear Block Lock-Bits Flowchart

START

BUS

OPERATION

COMMAND

COMMENTS

WRITE 60H

SR.7 =

YES

FULL STATUS

CHECK IF DESIRED

CLEAR BLOCK

LOCK-BITS COMPLETE

WRITE D0H

CLEAR BLOCK

LOCK-BITS

SUCCESSFUL

VPP RANGE

ERROR

READ STATUS

(see above)

SR.3 =

Write

Read

Standby

Clear Block

Lock-Bits Setup

Clear Block

Lock-Bits

Confirm

Data = 60H

Addr = X

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

Data = D0H

Addr = X

Write FFH after the Clear Block Lock-Bits operation to

place device in read array mode.

BUS

OPERATION

COMMAND

FULL STATUS CHECK PROCEDURE

COMMENTS

Standby

Check SR.3

1 = VPP Error Detect

Check SR.1

1 = Device Protect Detect

RP = VIH, Master Lock-Bit is Set

Check SR.4, 5

Both 1 = Command

Sequence Error

Check SR.5

1 = Clear Block Lock-Bit Error

SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status

If error is detected, clear the Status Register before attemping

retry or other error recovery.

28F008SC-11

READ STATUS REGISTER

YES

SR.1 =

SR.4, 5 =

SR.5 =

COMMAND

SEQUENCE

ERROR

DEVICE

PROTECT

ERROR

CLEAR BLOCK

LOCK-BITS ERROR

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