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LH28F008SC bảng dữ liệu(PDF) 24 Page - Sharp Corporation |
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LH28F008SC bảng dữ liệu(HTML) 24 Page - Sharp Corporation |
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24 / 38 page ![]() LH28F008SC 8M (1M × 8) Flash Memory 24 DC CHARACTERISTICS (Continued) SYM. PARAMETER V CC = 3.3 V V CC = 5 V UNIT TEST CONDITIONS NOTE MIN. MAX. MIN. MAX. V IL Input Low Voltage -0.5 0.8 -0.5 0.8 V 7 V IH Input High Voltage 2.0 V CC + 0.5 2.0 V CC + 0.5 V 7 V OL Output Low Voltage 0.4 0.45 V V CC = VCC MIN., I OL = 5.8 mA 3, 7 V OH 1 Output High Voltage (TTL) 2.4 2.4 V V CC = VCC MIN., I OH = 2.5 mA 3, 7 V OH 2 Output High Voltage (CMOS) 0.85 V CC 0.85 V CC V V CC = VCC MIN., I OH = 2.5 µA 4, 7 V CC - 0.4 V CC - 0.4 V V CC = VCC MIN., I OH = 100 µA V PPLK V PP Lockout during Normal Operations 1.5 1.5 V V PPH 1 V PP during Byte Write, Block Erase, or Lock- Bit Operations 3.0 3.6 V V PPH 2 V PP during Byte Write, Block Erase, or Lock- Bit Operations 4.5 5.5 4.5 5.5 V V PPH 3 V PP during Byte Write, Block Erase, or Lock- Bit Operations 11.4 12.6 11.4 12.6 V V LKO V CC Lockout Voltage 2.0 2.0 V V HH RP » Unlock Voltage 11.4 12.6 11.4 12.6 V Set Master Lock-Bit Override Master and Block Lock-Bit 8 NOTES: 1. All currents are in RMS unless otherwise noted. These currents are valid for all product versions (packages and speeds). Contact SHARP’s Application Support Hotline or your local sales office for information about typical specifications. 2. ICCWS and ICCES are specified with the device de-selected. If read or byte written while in erase suspend mode, the device’s current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. 3. Includes RY »/BY ». 4. Block erases, byte writes, and lock-bit configurations are inhibited when VPP ≤ VPPLK, and not guaranteed in the range between VPPLK (MAX.) and VPPH 1(MIN.), between V PPH 1(MAX.) and V PPH 2 (MIN.), between V PPH 2 (MAX.) and V PPH 3 (MIN.), and above V PPH 3 (MAX.). 5. Automatic Power Savings (APS) reduces typical ICCR to 1mA at 5 V VCC and 3 mA at 3.3 V VCC in static operation. 6. CMOS inputs are either VCC ± 0.2 V or GND ± 0.2 V. TTL inputs are either VIL or VIH. 7. Sampled, but not 100% tested. 8. Master lock-bit set operations are inhibited when RP » = VIH. Block lock-bit configuration operations are inhibited when the master lock bit is set and RP » = VIH. Block erases and byte writes are inhibited when the corresponding block-lock bit is set and RP » = VIH. Block erase, byte write, and lock-bit configuration operations are not guaranteed with VIH < RP » < VHH. |
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