900844 datasheet(88/118 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

900844

FUNCTIONAL DEVICE OPERATION

ADC SUBSYSTEM

INPUT POWER PATH REGISTERS AND BITS DESCRIPTION

ADC SUBSYSTEM

CONVERTER CORE

The ADC core is a 10 bit converter. The ADC core and logic run at an internally generated frequency of approximately

1.33 MHz. If an ADC conversion is requested while the PLL was not active, it will automatically be enabled by the ADC. A

32.768 kHz equivalent time base is derived from the 2.0 MHz clock to time ADC events. The ADC is supplied from VCORE. The

ADC core has an integrated auto calibration circuit which reduces the offset and gain errors.

MBATDET

Battery Detection Interrupt Signal Mask

x0 = Unmask

x1 = Mask

RSVD

7:6

Reserved

SCHRGINT (ADDR 0XD2 - R - DEFAULT VALUE: 0X00)

Reserved

SBATOVP

Input voltage over-voltage Status

x0 = Input voltage is lower than the limit (< VCHGCV + VOVRVOLT)

x1 = Input voltage is higher than the limit (> VCHGCV + VOVRVOLT)

STEMP

Battery temperature Status

x0 = Battery temperature is within valid window

x1 = Battery temperature is out of valid window

RSVD

Reserved

RSVD

Reserved

SBATDET

Battery Present Status Signal

x0 = Battery not present (VBAT < VTRKL)

x1 = Battery present (VBAT > VTRKL)

RSVD

7:6

Reserved

Table 56. FSL Charger Control Register Structure and Bits Description

Name

Bits

Description

FSLCHRGCNTL (ADDR 0X1D1 - R/W - DEFAULT VALUE: 0X13)

RSVD

Reserved

COINCHEN

Coin cell Charger Enable/Disable

x0 = Disable

x1 = Enable (Default)

VCOIN

4:2

Coin cell Charger Output Voltage Setting

x0 = 2.5 V

x1 = 2.7 V

x2 = 2.8 V

x3 = 2.9 V

x4 = 3.0 V (Default)

x5 = 3.1 V

x6 = 3.2 V

x7 = 3.3 V

Reserved

7:5

Reserved

Table 55. Input Power Interrupt/Mask Registers Structure and Bits Description

Name

Bits

Description

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