900844 datasheet(42/118 Pages) FREESCALE

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Analog Integrated Circuit Device Data

Freescale Semiconductor

900844

FUNCTIONAL DEVICE OPERATION

SYSTEM CONTROL INTERFACE

TEST MODES

Test Mode Configuration

During evaluation and testing, the IC can be configured for normal operation or test mode via the ICTEST pin and other register

configurations. Details of Test mode programmability are not documented herein, but should be referenced from other Design

for Test documentation.

Test modes are for Freescale use only, and must not be accessed in applications. In test modes, signals are multiplexed on

existing functional pins. The ICTEST pin must therefore be tied to ground (for normal operation) at the board level, in product

applications

Test mode also disables the thermal protection for high temperature op life testing. A proprietary protocol is included for scan

chain test configurations, which reuses the SPI pins.

In-package Trimming

During IC final test, several parameters are trimmed in the package, such as the main bandgap, and other precision analog

functions. Trim registers are for Freescale use only and must not be accessed in product applications. Fuse programming

circuitry will be blocked during normal and test mode operation.

Table 17. PLL Control Register Structure and Bit Description

Name

Bits

Description

FSLPLLCNTL (ADDR 0x1E4 - R/W - Default Value: 0x1B)

PLLDIVIDE

2:0

PLL Divide Ratio and Effective VCO Frequency Settings

x0 = 112, 3.670 MHz

x1 = 116, 3.801 MHz

x2 = 120, 3.932 MHz

x3 = 124, 4.063 MHz

x4 = 128, 4.194 MHz

x5 = 132, 4.325 MHz

x6 = 136, 4.456 MHz

x7 = 140, 4.588 MHz

PLL16MEN

16 MHz frequency enable

x0 = 16 MHz clock disabled

x1 = 16 MHz clock enabled and PLL enabled

PLLEN

PLL Enable, even if there is no block requesting a clock

x0 = PLL enabled based on device enables only

x1 = PLL enabled

Reserved

7:5

Reserved

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