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IMX28AEC bảng dữ liệu(PDF) 52 Page - Freescale Semiconductor, Inc

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Giải thích chi tiết về linh kiện  Processors Data Sheet for Automotive Products High assurance boot
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IMX28AEC bảng dữ liệu(HTML) 52 Page - Freescale Semiconductor, Inc

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i.MX28 Applications Processors Data Sheet for Automotive Products, Rev. 1
52
Freescale Semiconductor
3.5.13
SPDIF AC Timing
SPDIF data is sent using bi-phase marking code. When encoding, the SPDIF data signal is modulated by
a clock that is twice the bit rate of the data signal.
The following Table 57 shows SPDIF timing parameters, including the timing of the modulating Tx clock
(spdif_clk) in SPDIF transmitter as shown in the Figure 35.
Figure 35. spdif_clk Timing
Table 56. SAIF Receiver Timing with Internal Clock
ID
Parameter
Min.
Max.
Unit
SS1
BITCLK period
81.4
—
ns
SS2
BITCLK high period
36.0
—
ns
SS3
BITCLK rise time
—
6.0
ns
SS4
BITCLK low period
36.0
—
ns
SS5
BITCLK fall time
—
6.0
ns
SS14
BITCLK high to LRCLK high
—
15.0
ns
SS15
BITCLK high to LRCLK low
—
15.0
ns
SS16
SDATA setup time before BITCLK high
10.0
—
ns
SS17
SDATA hold time after BITCLK high
0.0
—
ns
Table 57. SPDIF Timing
Characteristics
Symbol
Timing Parameter Range
Unit
Min
Max
SPDIFOUT output (Load = 30pf)
•Skew
• Transition Rising
• Transition Falling
—
—
—
—
—
—
1.5
13.6
18.0
ns
Modulating Tx clock (spdif_clk) period
spclkp
81.4
—
ns
spdif_clk high period
spclkph
65.1
—
ns
spdif_clk low period
spclkpl
65.1
—
ns
spdif_clk
(Input)
spclkp
spclkph
spclkpl



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