CYWUSB6953_10 datasheet(7/68 Pages) CYPRESS

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CYRF69103

Document #: 001-07611 Rev *F

Page 7 of 68

8. Functional Block Overview

All the blocks that make up the PRoC LP are presented in this

section.

8.1 2.4 GHz Radio

The radio transceiver is a dual conversion low IF architecture

optimized for power and range/robustness. The radio employs

channel matched filters to achieve high performance in the

presence of interference. An integrated Power Amplifier (PA)

provides up to +4 dBm transmit power, with an output power

control range of 34 dB in seven steps. The supply current of the

device is reduced as the RF output power is reduced.

8.2 Frequency Synthesizer

Before transmission or reception may commence, it is necessary

for the frequency synthesizer to settle. The settling time varies

depending on channel; 25 fast channels are provided with a

maximum settling time of 100

μs.

The “fast channels” (<100

μs settling time) are every 3rd

frequency, starting at 2400 MHz up to and including 2472 MHz

(that is, 0,3,6,9…….69 and 72).

8.3 Baseband and Framer

The baseband and framer blocks provide the DSSS encoding

and decoding, SOP generation and reception and CRC16

generation and checking, and EOP detection and length field.

8.3.1 Data Transmission Modes and Data Rates

The SoC supports four different data transmission modes:

■ In GFSK mode, data is transmitted at 1 Mbps, without any

DSSS.

■ In 8DR mode, 8 bits are encoded in each DATA_CODE_ADR

derived code symbol transmitted.

■ In DDR mode, 2 bits are encoded in each DATA_CODE_ADR

derived code symbol transmitted (as in the CYWUSB6934 DDR

mode).

■ In SDR mode, 1 bit is encoded in each DATA_CODE_ADR

derived code symbol transmitted (as in the CYWUSB6934

standard modes).

Both 64-chip and 32-chip DATA_CODE_ADR codes are

supported. The four data transmission modes apply to the data

after the SOP. In particular the length, data, and CRC16 are all

sent in the same mode. In general, lower data rates reduces

packet error rate in any given environment.

The CYRF69103 IC supports the following data rates:

■ 1000 kbps (GFSK)

■ 250 kbps (32-chip 8DR)

■ 125 kbps (64-chip 8DR)

■ 62.5 kbps (32-chip DDR)

■ 31.25 kbps (64-chip DDR)

■ 15.625 kbps (64-chip SDR)

Lower data rates typically provide longer range and/or a more

robust link.

PACTL

Control for external PA or Radio GPIO

P1.6

GPIO

VIO

1.8V to 3.6V to main power supply rail for Radio I/O

RST

Radio Reset. Connected to pin 40 with 0.47

μF. Must have a RST=HIGH event the very first time

power is applied to the radio otherwise the state of the radio control registers is unknown

P1.7

GPIO

VDD1.8

Regulated logic bypass. Connected to 0.47

μF to GND

L/D

Inductor/Diode connection for Boost. When Internal PMU is not being used connect L/D to GND.

P0.7

GPIO

Vbat0

Connected to1.8V to 3.6V main power supply, through 0.047

μF bypass C

VREG

Boost regulator output voltage feedback

E-pad

Must be connected to ground

Corner Tabs

Do Not connect corner tabs

Table 7-1. Pin Definitions (continued)

Name

Description

Table 8-1. Internal PA Output Power Step Table

PA Setting

Typical Output Power (dBm)

7+4

5–5

–10

–15

–20

–25

–30

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