CYWUSB6953_10 datasheet(39/68 Pages) CYPRESS

39 / 68 page

CYRF69103

Document #: 001-07611 Rev *F

Page 39 of 68

Bit 7

Reserved

Bit 6

see Section 19.2.1

Bit 5

see Section 19.2.2

Bit 4

see Section 19.2.3

Bit 3

Reserved

Bit 2

see Section 19.2.5

Bit 1

see Section 19.2.6

Bit 0

see Section 19.2.7

Table 19-5. P0.3–P0.4 Configuration (P03CR–P04CR) [0x08–0x09] [R/W]

Bit #

Field

Reserved

Int Act Low

TTL Thresh

Reserved

Open Drain

Pull up

Enable

Output

Enable

Read/Write

–

R/W

–R/W

R/W

Default

These registers control the operation of pins P0.3–P0.4 respectively. These pins are shared between the P0.3–P0.4 GPIOs and

the INT1–INT2. The INT1–INT2 interrupts are different than all the other GPIO interrupts. These pins are connected directly to

the interrupt controller to provide three edge-sensitive interrupts with independent interrupt vectors. These interrupts occur on

a rising edge when Int act Low is clear and on a falling edge when Int act Low is set. These pins are enabled as interrupt sources

in the interrupt controller registers (Table 21-8 on page 54 and Table 21-6 on page 53).

To use these pins as interrupt inputs, configure them as inputs by clearing the corresponding Output Enable. If the INT1–INT2

pins are configured as outputs with interrupts enabled, firmware can generate an interrupt by writing the appropriate value to the

P0.3, and P0.4 data bits in the P0 Data Register.

Regardless of whether the pins are used as Interrupt or GPIO pins the Int Enable, Int act Low, TTL Threshold, Open Drain, and

Pull up Enable bits control the behavior of the pin.

The P0.3/INT1–P0.4/INT2 pins are individually configured with the P03CR (0x08), and P04CR (0x09) respectively.

Note Changing the state of the Int Act Low bit can cause an unintentional interrupt to be generated. When configuring these

interrupt sources, it is best to follow the following procedure:

1. Disable interrupt source

2. Configure interrupt source

3. Clear any pending interrupts from the source

4. Enable interrupt source

Table 19-6. P0.7 Configuration (P07CR) [0x0C] [R/W]

Bit #

Field

Reserved

Int Enable

Int Act Low

TTL Thresh

Reserved

Open Drain

Pull up

Enable

Output

Enable

Read/Write

–

R/W

–

R/W

Default

00000000

his register controls the operation of pin P0.7.

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