MPC8544E datasheet(72/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

High-Speed Serial Interfaces (HSSI)

Figure 54. Single-Ended Measurement Points for Rise and Fall Time Matching

The other detailed AC requirements of the SerDes reference clocks is defined by each interface protocol

based on application usage. Refer to the following sections for detailed information:

•

Section 8.3.1, “The DBWO Signal”

•

Section 17.2, “AC Requirements for PCI Express SerDes Clocks”

16.2.4.1

Spread Spectrum Clock

SD1_REF_CLK/SD1_REF_CLK were designed to work with a spread spectrum clock (+0 to –0.5%

spreading at 30–33 kHz rate is allowed), assuming both ends have same reference clock. For better results,

a source without significant unintended modulation should be used.

SD2_REF_CLK/SD2_REF_CLK are not intended to be used with, and should not be clocked by, a spread

spectrum clock source.

16.3

SerDes Transmitter and Receiver Reference Circuits

Figure 55 shows the reference circuits for SerDes data lane’s transmitter and receiver.

Figure 55. SerDes Transmitter and Receiver Reference Circuits

The DC and AC specification of SerDes data lanes are defined in the section below (PCI Express or

SGMII) in this document based on the application usage:

•

Section 8.3, “SGMII Interface Electrical Characteristics”

•

Section 17, “PCI Express”

Please note that external AC Coupling capacitor is required for the above serial transmission protocols

with the capacitor value defined in specification of each protocol section.

SDn_REF_CLK

VCROSS MEDIAN

VCROSS MEDIAN + 100 mV

VCROSS MEDIAN – 100 mV

TFALL

TRISE

Receiver

Transmitter

SD1_TXn or

SD2_TXn

SD1_RXn or

SD2_RXn

SD1_TXn or

SD2_TXn

SD1_RXn or

SD2_RXn

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