MPC8544E datasheet(33/117 Pages) FREESCALE

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MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5

Freescale Semiconductor

Enhanced Three-Speed Ethernet (eTSEC), MII Management

8.5.2.2

GMII Receive AC Timing Specifications

Table 31 provides the GMII receive AC timing specifications.

Figure 14 provides the AC test load for eTSEC.

Figure 14. eTSEC AC Test Load

Figure 15 shows the GMII receive AC timing diagram.

Figure 15. GMII Receive AC Timing Diagram

8.6

MII AC Timing Specifications

This section describes the MII transmit and receive AC timing specifications.

Table 31. GMII Receive AC Timing Specifications

At recommended operating conditions with L/TVDD of 3.3 V ± 5% or 2.5 V ± 5%

Parameter/Condition

Symbol1

Min

Typ

Max

Unit

Notes

RX_CLK clock period

tGRX

—

8.0

—ns—

RX_CLK duty cycle

tGRXH/tGRX

—

RXD[7:0], RX_DV, RX_ER setup time to RX_CLK

tGRDVKH

2.0

—

—ns—

RX_CLK to RXD[7:0], RX_DV, RX_ER hold time

tGRDXKH

0.5

—

—ns—

RX_CLK clock rise (20%–80%)

tGRXR

——

1.0

—

RX_CLK clock fall time (80%–20%)

tGRXF

——

1.0

—

Note:

1. The symbols used for timing specifications follow the pattern of t(first two letters of functional block)(signal)(state)(reference)(state) for

inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive

timing (GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K)

going to the high state (H) or setup time. Also, tGRDXKL symbolizes GMII receive timing (GR) with respect to the time data

input signals (D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note that, in

general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.

For example, the subscript of tGRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention

is used with the appropriate letter: R (rise) or F (fall).

Output

Z0 = 50 Ω

LVDD/2

RL = 50 Ω

RX_CLK

RXD[7:0]

tGRDXKH

tGRX

tGRXH

tGRXR

tGRXF

tGRDVKH

RX_DV

RX_ER

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