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MPC8544E bảng dữ liệu(PDF) 28 Page - Freescale Semiconductor, Inc |
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MPC8544E bảng dữ liệu(HTML) 28 Page - Freescale Semiconductor, Inc |
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28 / 117 page ![]() MPC8544E PowerQUICC III Integrated Processor Hardware Specifications, Rev. 5 28 Freescale Semiconductor Enhanced Three-Speed Ethernet (eTSEC), MII Management 8.4 SGMII AC Timing Specifications This section describes the SGMII transmit and receive AC timing specifications. Transmitter and receiver characteristics are measured at the transmitter outputs (SD2_TX[n] and SD2_TX[n]) or at the receiver inputs (SD2_RX[n] and SD2_RX[n]) as depicted in Figure 10, respectively. 8.4.1 SGMII Transmit AC Timing Specifications Table 26 provides the SGMII transmit AC timing targets. A source synchronous clock is not provided. Input differential voltage LSTS = 0 Vrx_diffpp 100 — 1200 mV 2, 4 LSTS = 1 175 — Loss of signal threshold LSTS = 0 Vlos 30 — 100 mV 3, 4 LSTS = 1 65 — 175 Input AC common mode voltage Vcm_acpp —— 100 mV 5. Receiver differential input impedance Zrx_diff 80 — 120 Ω — Receiver common mode input impedance Zrx_cm 20 — 35 Ω — Common mode input voltage Vcm xcorevss — xcorevss V 6 Notes: 1. Input must be externally AC-coupled. 2. VRX_DIFFp-p is also referred to as peak-to-peak input differential voltage 3. The concept of this parameter is equivalent to the electrical idle detect threshold parameter in PCI Express. Refer to Section 17.4.3, “Differential Receiver (RX) Input Specifications,” for further explanation. 4. The LSTS shown in this table refers to the LSTSCD bit field of MPC8544E SerDes 2 control register 1. 5. VCM_ACp-p is also referred to as peak-to-peak AC common mode voltage. 6. On-chip termination to SGND_SRDS2 (xcorevss). Table 26. SGMII Transmit AC Timing Specifications At recommended operating conditions with XVDD_SRDS2 = 1.0 V ± 5%. Parameter Symbol Min Typ Max Unit Notes Deterministic jitter JD — — 0.17 UI p-p — Total jitter JT — — 0.35 UI p-p — Unit interval UI 799.92 800 800.08 ps 2 VOD fall time (80%–20%) tfall 50 — 120 ps — VOD rise time (20%–80%) trise 50 — 120 ps — Notes; 1. Source synchronous clock is not supported. 2. Each UI value is 800 ps ± 100 ppm. Table 25. DC Receiver Electrical Characteristics (continued) Parameter Symbol Min Typ Max Unit Notes |
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