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MPC8315ECVRAGDA bảng dữ liệu(PDF) 24 Page - Freescale Semiconductor, Inc |
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MPC8315ECVRAGDA bảng dữ liệu(HTML) 24 Page - Freescale Semiconductor, Inc |
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24 / 112 page ![]() MPC8315E PowerQUICC™ II Pro Processor Hardware Specifications, Rev. 0 24 Freescale Semiconductor DUART Figure 9 provides the AC test load for the DDR bus. Figure 9. DDR AC Test Load 8DUART This section describes the DC and AC electrical specifications for the DUART interface. 8.1 DUART DC Electrical Characteristics Table 21 lists the DC electrical characteristics for the DUART interface. 8.2 DUART AC Electrical Specifications Table 22 lists the AC timing parameters for the DUART interface. 9 Ethernet: Three-Speed Ethernet, MII Management This section provides the AC and DC electrical characteristics for three-speed, 10/100/1000, and MII management. Table 21. DUART DC Electrical Characteristics Parameter Symbol Min Max Unit High-level input voltage VIH 2.1 NVDD + 0.3 V Low-level input voltage NVDD VIL –0.3 0.8 V High-level output voltage, IOH = –100 μAVOH NVDD – 0.2 — V Low-level output voltage, IOL = 100 μAVOL —0.2 V Input current (0 V ≤VIN ≤ NVDD) IIN —± 5 μA Table 22. DUART AC Timing Specifications Parameter Value Unit Notes Minimum baud rate 256 baud — Maximum baud rate > 1,000,000 baud 1 Oversample rate 16 — 2 Notes: 1. Actual attainable baud rate is limited by the latency of interrupt processing. 2. The middle of a start bit is detected as the eighth sampled 0 after the 1-to-0 transition of the start bit. Subsequent bit values are sampled each sixteenth sample. Output Z0 = 50 Ω GVDD/2 RL = 50 Ω |
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