PCA9620 datasheet(40/71 Pages) NXP

40 / 71 page

PCA9620

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Product data sheet

Rev. 1 — 9 December 2010

40 of 71

NXP Semiconductors

PCA9620

Universal LCD driver for low multiplex rates

7.7 Segment outputs

The LCD drive section includes 60 segment outputs (S0 to S59) which must be connected

directly to the LCD. The segment output signals are generated based on the multiplexed

backplane signals and with data resident in the display register. When less than

60 segment outputs are required, the unused segment outputs must be left open-circuit.

7.8 Display register

The display register holds the display data while the corresponding multiplex signals are

generated.

7.9 Display RAM

The display RAM is a static 60

× 8-bit RAM which stores LCD data. Logic 1 in the RAM bit

map indicates the on-state of the corresponding LCD element; similarly, logic 0 indicates

the off-state.

There is a one-to-one correspondence between

• the bits in the RAM bitmap and the LCD elements

• the RAM columns and the segment outputs

• the RAM rows and the backplane outputs.

The display RAM bit map, Figure 30, shows row 0 to row 7 which correspond with the

backplane outputs BP0 to BP7, and column 0 to column 59 which correspond with the

segment outputs S0 to S59. In multiplexed LCD applications the data of each row of the

display RAM is time-multiplexed with the corresponding backplane (row 0 with BP0, row 1

with BP1 and so on).

When display data is transmitted to the PCA9620 the display bytes received are stored in

the display RAM in accordance with the selected LCD multiplex drive mode. The data is

stored as it arrives and does not wait for the acknowledge cycle as with the commands.

Depending on the current multiplex drive mode, data is stored singularly, in pairs,

quadruples, sextuples or bytes.

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