PCA9620 datasheet(31/71 Pages) NXP

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PCA9620

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Product data sheet

Rev. 1 — 9 December 2010

31 of 71

NXP Semiconductors

PCA9620

Universal LCD driver for low multiplex rates

When eight backplanes are provided in the LCD, the 1:8 multiplex drive mode applies, as

shown in Figure 21 and Figure 22.

7.4.3 VLCD generation

VLCD can be generated and controlled on the chip by using software commands. When

the internal charge pump is used, the programmed VLCD is available on pin VLCD. The

charge pump generates a VLCD of up to 3 × VDD2.

The charge pump can be enabled or disabled with the CPE bit (see Table 8 on page 7).

With bit CPC the charge pump multiplier setting can be configured.

The final value of VLCD is a combination of the programmed VPR[7:0] value and the output

of the temperature compensation block, VT[7:0]. The system is shown in Figure 23.

In Equation 6 the main parameters are the programmed digital value term and the

compensated temperature term.

(6)

1. VPR[7:0] is the binary value of the programmed voltage.

2. VT[7:0] is the binary value of the temperature compensated voltage. Its value comes

from the temperature compensation block and is a two’s complement which has the

value 0h at 20

°C.

3. m and n are fixed values (see Table 27).

Figure 24 shows how VLCD changes with the programmed value of VPR[7:0].

Fig 23. VLCD generation including temperature compensation

013aaa257

TEMPERATURE

READOUT

−40

+80

+20

+50

TEMPERATURE

0 OFFSET

SLA

SLB

SLC

SLD

VPR[7:0]

VLCD

Table 27.

Parameters of VLCD generation

Symbol

Value

Unit

n0.03

LCD

VPR 7:0

[] VT 7:0

[]

[] n

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