7549 datasheet(26/86 Pages) RENESAS

26 / 86 page

Rev.2.02

Mar 31, 2009

Page 24 of 81

REJ03B0202-0202

7549 Group

Fig 21. Interrupt sequence

Fig 22. Timing of interrupt request generation, interrupt request bit, and interrupt acceptance

<Notes>

The interrupt request bit may be set to “1” in the following cases.

•INT0 interrupt edge selection bit

(bit 0 of Interrupt edge selection register (address 003A16))

•INT1 interrupt edge selection bit

(bit 1 of Interrupt edge selection register)

If it is not necessary to generate an interrupt synchronized with

these settings, take the following sequence.

(1)Set the corresponding enable bit to “0” (disabled).

(2)Set the interrupt edge selection bit (the active edge switch

bit) or the interrupt source bit.

(3)Set the corresponding interrupt request bit to “0” after one

or more instructions have been executed.

(4)Set the corresponding interrupt enable bit to “1” (enabled).

SYNC

Push onto stack

Vector fetch

Address bus

Data bus

Execute interrupt

routine

S,SPS

S-1,SPS S-2,SPS

AL,AH

Not used

PCH

PCL

SYNC : CPU operation code fetch cycle

(This is an internal signal that cannot be observed from the external unit.)

BL, BH: Vector address of each interrupt

AL, AH: Jump destination address of each interrupt

SPS

: “0016” or “0116”

([SPS] is a page selected by the stack page selection bit of CPU mode register.)

(1) The interrupt request bit for an interrupt request generated during period 1 is set to “1” at timing point IR1.

(2) The interrupt request bit for an interrupt request generated during period 2 is set to “1” at timing point IR1 or IR2.

The timing point at which the bit is set to “1” varies depending on conditions. When two or more interrupt

requests are generated during the period 2, each request bit may be set to “1” at timing point IR1 or IR2

separately.

T1 T2 T3 : Interrupt acceptance timing points

IR1 IR2 : Timings points at which the interrupt request bit is set to “1”.

Note : Period 2 indicates the last

φ cycle during one instruction cycle.

IR1 T2

SYNC

IR2 T3

Internal clock

Instruction cycle

Push onto stack

Vector fetch

Instruction cycle

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