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XIO2001IPNP bảng dữ liệu(PDF) 101 Page - Texas Instruments

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Giải thích chi tiết về linh kiện  PCI Express??to PCI Bus Translation Bridge
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XIO2001
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SCPS212D – MAY 2009 – REVISED JANUARY 2010
5.13 Secondary Error Capabilities and Control Register
The secondary error capabilities and control register allows the system to monitor and control the
secondary advanced error reporting capabilities. See Table 5-11 for a complete description of the register
contents.
PCI Express extended register offset: 138h
Register type:
Read-only
Default value:
0000 0000h
BIT NUMBER
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
BIT NUMBER
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
RESET STATE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Table 5-11. Secondary Error Capabilities and Control Register Description
BIT
FIELD NAME
ACCESS
DESCRIPTION
31:5
RSVD
R
Reserved. Return 000 0000 0000 0000 0000 0000 0000b when read.
4:0(1)
SEC_FIRST_ERR
RU
First error pointer. This 5-bit value reflects the bit position within the secondary
uncorrectable error status register (offset 12Ch, see Section 5.10) corresponding to the
class of the first error condition that was detected.
(1)
These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.
Copyright © 2009–2010, Texas Instruments Incorporated
PCI Express Extended Configuration Space
101
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