XIO2001IPNP datasheet(85/131 Pages) TI

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XIO2001

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SCPS212D – MAY 2009 – REVISED JANUARY 2010

Table 4-46. Serial IRQ Mode Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

7:4

RSVD

Reserved. Returns 0h when read.

Start frame pulse width. Sets the width of the start frame for a SERIRQ stream.

00 = 4 clocks (default)

3:2(1)

START_WIDTH

01 = 6 clocks

10 = 8 clocks

11 = Reserved

Poll mode. This bit selects between continuous and quiet mode.

1(1)

POLLMODE

0 = Continuous mode (default)

1 = Quiet mode

RW Drive mode. This bit selects the behavior of the serial IRQ controller during the

recovery cycle.

0(1)

DRIVEMODE

0 = Drive high (default)

1 = 3-state

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

4.73 Serial IRQ Edge Control Register

This register controls the edge mode or level mode for each IRQ in the serial IRQ stream. See Table 4-47

for a complete description of the register contents.

PCI register offset:

E2h

Read/Write

Default value:

0000h

BIT NUMBER

RESET STATE

Table 4-47. Serial IRQ Edge Control Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

IRQ 15 edge mode

15(1)

IRQ15_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 14 edge mode

14(1)

IRQ14_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 13 edge mode

13(1)

IRQ13_MODE

0 = Edge mode (default)

1 = Level mode

IRQ 12 edge mode

12(1)

IRQ12_MODE

0 = Edge mode (default)

1 = Level mode

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

Classic PCI Configuration Space

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