XIO2001IPNP datasheet(95/131 Pages) TI

95 / 131 page

XIO2001

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SCPS212D – MAY 2009 – REVISED JANUARY 2010

Table 5-4. Uncorrectable Error Severity Register Description (continued)

BIT

FIELD NAME

ACCESS

DESCRIPTION

12 (1)

PSN_TLP_SEVR

Poisoned TLP severity

0 = Error condition is signaled using ERR_NONFATAL

1 = Error condition is signaled using ERR_FATAL

11:6

RSVD

Reserved. Returns 000 000b when read.

SD_ERROR_SEVR

SD error severity. Not supported, returns 1b when read.

4 (1)

DLL_ERROR_SEVR

Data link protocol error severity

0 = Error condition is signaled using ERR_NONFATAL

1 = Error condition is signaled using ERR_FATAL

3:1

RSVD

Reserved. Retirms 000b wjem read/

RSVD

Reserved. Returns 1h when read.

5.6

Correctable Error Status Register

The correctable error status register reports the status of individual errors as they occur. Software may

only clear these bits by writing a 1b to the desired location. See Table 5-5 for a complete description of

the register contents.

PCI Express extended register offset:

110h

Read-only, Read/Clear

Default value:

0000 0000h

BIT NUMBER

RESET STATE

BIT NUMBER

RESET STATE

Table 5-5. Correctable Error Status Register Description

BIT

FIELD NAME

ACCESS

DESCRIPTION

31:14

RSVD

Reserved. Returns 000 0000 0000 0000 0000b when read.

13(1)

ANFES

RCU

Advisory Non-Fatal Error Status. This bit is asserted when an Advisor Non-Fatal Error has

been reported.

12 (1)

REPLAY_TMOUT

RCU

Replay timer time-out. This bit is asserted when the replay timer expires for a pending request

or completion that has not been acknowledged.

11:9

RSVD

Reserved. Returns 000b when read.

8 (1)

REPLAY_ROLL

RCU

REPLAY_NUM rollover. This bit is asserted when the replay counter rolls over after a pending

request or completion has not been acknowledged.

7 (1)

BAD_DLLP

RCU

Bad DLLP error. This bit is asserted when an 8b/10b error was detected by the PHY during

the reception of a DLLP.

6 (1)

BAD_TLP

RCU

Bad TLP error. This bit is asserted when an 8b/10b error was detected by the PHY during the

reception of a TLP.

5:1

RSVD

Reserved. Returns 00000b when read.

0 (1)

RX_ERROR

RCU

Receiver error. This bit is asserted when an 8b/10b error is detected by the PHY at any time.

(1)

These bits are reset by a PCI Express reset (PERST), a GRST, or the internally-generated power-on reset.

PCI Express Extended Configuration Space

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