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ADS58C48IPFPR bảng dữ liệu(PDF) 18 Page - Texas Instruments

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tên linh kiện ADS58C48IPFPR
Giải thích chi tiết về linh kiện  Quad Channel IF Receiver with SNRBoost 3G
PDF  70 Pages
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ADS58C48IPFPR bảng dữ liệu(HTML) 18 Page - Texas Instruments

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ADS58C48
SLAS689 – MAY 2010
www.ti.com
DESCRIPTION OF SERIAL REGISTERS
ADDRS
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
A7-A0 IN
VALUE
HEX
AFTER
RESET
00
00
0
0
0
0
0
0
<RESET>
<READOUT>
D1
<RESET>
1
Software reset applied – resets all internal registers to their default values and self-clears to 0.
D0
<READOUT>
0
Serial readout of registers is disabled. Pin SDOUT is put in high-impedance state.
1
Serial readout is enabled. Pin SDOUT functions as serial data readout with CMOS logic levels,
running off DRVDD supply.
See Serial Register Readout section.
ADDRS
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
A7-A0 IN
VALUE
HEX
AFTER
RESET
01
00
<LVDS SWING>
0
0
D7-D2
<LVDS SWING> LVDS swing programmability
000000
Default LVDS swing; ±350mV with external 100-
Ω termination
011011
LVDS swing increases to ±410mV
110010
LVDS swing increases to ±465mV
010100
LVDS swing increases to ±570mV
111110
LVDS swing decreases to ±200mV
001111
LVDS swing decreases to ±125mV
Other
Do not use
combinations
ADDRS
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
A7-A0 IN
VALUE
HEX
AFTER
RESET
25
00
<GAIN CH B>
0
<TEST PATTERNS – CH B>
ADDRS
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
A7-A0 IN
VALUE
HEX
AFTER
RESET
26
00
0
<CHB SNRBoost FILTER #>
ADDRS
DEFAULT
D7
D6
D5
D4
D3
D2
D1
D0
A7-A0 IN
VALUE
HEX
AFTER
RESET
28
00
0
<SNRBoost
0
0
0
0
0
0
CH B ON>
18
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Copyright © 2010, Texas Instruments Incorporated
Product Folder Link(s) :ADS58C48



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