ADS58C48IPFPR datasheet(30/70 Pages) TI

30 / 70 page

ADS58C48

SLAS689 – MAY 2010

www.ti.com

NUMBER

PIN NAME

DESCRIPTION

OF PINS

TYPE

NUMBER

INC_P,

Differential analog input, Channel C

34, 35

INC_M

IND_P,

Differential analog input, Channel D

37, 38

IND_M

Outputs the common-mode voltage (0.95 V) that can be used externally to bias

the analog input pins.

RESET

Serial interface RESET input.

The user must initialize internal registers through hardware RESET by applying a

high-going pulse on this pin or by using software reset option. Refer to SERIAL

INTERFACE section. The pin has an internal 100k

Ω pull-down resistor.

SCLK

Serial interface clock input. The pin has an internal 100-k

Ω pull-down resistor.

SDATA

Serial interface data input. The pin has an internal 100-k

Ω pull-down resistor.

SEN

Serial interface enable input. The pin has an internal 100-k

Ω pull-up resistor to

DRVDD

SDOUT

This pin functions as serial interface register readout, when the <READOUT> bit

is enabled.

When <READOUT> = 0, this pin is put in high impedance state.It is a CMOS

output pin running off DRVDD supply.

PDN

Power down control pin. The pin has an internal 150-k

Ω pull-down resistor to

DRGND.

SNRB_1,

SNRBoost 3G control pins. Each pin has an internal 150-k

Ω pull-down resistor to

41, 40

SNRB_2

DRGND.

CLKOUT

CMOS output clock

CHA_D0 to

Channel A ADC output data bits, CMOS levels

Refer to

CHA_D10

Figure 10

CHB_D0 to

Channel B ADC output data bits, CMOS levels

CHB_D10

CHC_D0 to

Channel C ADC output data bits, CMOS levels

CHC_D10

CHD_D0 to

Channel D ADC output data bits, CMOS levels

CHD_D10

DRVDD

1.8 V, digital supply

1,60, 69, 70

DNC

Do not connect

4, 42, 54, 67,

PAD

MUST be connected to ground.

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