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ADS58C48IPFPR bảng dữ liệu(PDF) 7 Page - Texas Instruments

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tên linh kiện ADS58C48IPFPR
Giải thích chi tiết về linh kiện  Quad Channel IF Receiver with SNRBoost 3G
PDF  70 Pages
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ADS58C48IPFPR bảng dữ liệu(HTML) 7 Page - Texas Instruments

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Dn_Dn+1_P
DAP/DBP
Dn_Dn+1_M
DAM/DBM
GND
GND
V
* With external 100-
termination
W
V
OCM
Logic 0
V
*
ODL
Logic 1
V
*
ODH
T0334-03
ADS58C48
www.ti.com
SLAS689 – MAY 2010
DIGITAL CHARACTERISTICS
The DC specifications refer to the condition where the digital outputs are not switching, but are permanently at a valid logic
level 0 or 1. AVDD = 1.8 V, DRVDD = 1.8 V
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL INPUTS – RESET, SCLK, SDATA, SEN, SNRB_1, SNRB_2 and PDN
High-level input voltage
RESET, SCLK, SDATA and SEN support
1.3
V
1.8 V and 3.3 V CMOS logic levels.
Low-level input voltage
0.4
V
High-level input
SDATA, SCLK(1)
VHIGH = 1.8 V
10
µA
current
SEN(2)
VHIGH = 1.8 V
0
µA
Low-level input
SDATA, SCLK
VLOW = 0 V
0
µA
current
SEN
VLOW = 0 V
–10
µA
DIGITAL OUTPUTS – CMOS INTERFACE (CHx_Dn, SDOUT)
High-level output voltage
DRVDD – 0.1
DRVDD
V
Low-level output voltage
0
0.1
V
DIGITAL OUTPUTS – LVDS INTERFACE (CHx<>P/M, CLKOUTP/M)
VODH, High-level output voltage
(3)
Standard swing LVDS
275
350
425
mV
VODL, Low-level output voltage
(3)
Standard swing LVDS
–425
–350
–275
mV
VODH, High-level output voltage
(3)
Low swing LVDS(4)
200
mV
VODL, Low-level output voltage
(3)
Low swing LVDS(4)
–200
mV
VOCM, Output common-mode voltage
0.9
1.05
1.25
V
(1)
SDATA, SCLK have internal 170-k
Ω pull-down resistor.
(2)
SEN has internal 170-k
Ω pull-up resistor to AVDD.
(3)
With external 100-
Ω termination.
(4)
See the LVDS Output Data and Clock Buffers section in the Application Information.
Figure 2. LVDS Output Voltage Levels
Copyright © 2010, Texas Instruments Incorporated
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